公开(公告)号：EP0414818A1

公开(公告)日：1991-03-06

申请号：EP89907900.0

申请日：1989-03-16

申请人： AlliedSignal Inc.

发明人： BERKOVICH, Semyon

IPC分类号： G11C15 ,  G06F13

CPC分类号： G06F13/376

摘要： On décrit un appareil et un procédé de transmission de données à partir d'une pluralité d'émetteurs (32, 38, 42) vers un récepteur (52) par un seul canal de communication (50). Ce système comporte un module de mémoire associative (12, 13, 14) pour chaque émetteur (32, 38, 42), ledit module (12, 13, 14) comprenant une mémoire (68) et une unité de commande (67) et ladite mémoire (68) pouvant être une mémoire à accès sélectif (68) ou une mémoire associative (68'). Cette invention permet de résoudre le problème que pose la transmission par le canal de communication (50), d'un mot-données par émetteur (32, 38, 42) juste avant que l'un des émetteurs ne transmette un second mot par le canal de communication.

公开(公告)号：EP0340344A2

公开(公告)日：1989-11-08

申请号：EP88121548.7

申请日：1988-12-23

申请人： International Business Machines Corporation

发明人： Sweeney, Michael Arthur

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/14 ,  G06F13/376

摘要： In processing a priority queue, the elements are kept in an unsorted stack and are searched for the next highest priority element only after the highest priority element has been read from the holding register. Each time a new element is written into the queue, a comparison is made of the priority of the new element with the priority of the existing element in the holding register. If the new element has a higher priority, then the existing element in the holding register is written onto the top of the stack. Alternately, if the element in the holding register has the higher priority, then the new element is written onto the top of the stack. This assures that the holding register always contains the element having the highest priority. Therefore, a read of the priority queue by reading the contents of the holding register guarantees that the highest priority element is there and it can be accessed immediately without further searching the queue.

摘要翻译： 在处理优先级队列时，元素保持在未排序的堆栈中，并且仅在从保持寄存器读取最高优先级元素之后才搜索下一个最高优先级元素。 每当将新元素写入队列时，将比较新元素的优先级，并保留在保留寄存器中的现有元素的优先级。 如果新元素具有较高的优先级，则保持寄存器中的现有元素将被写入堆栈顶部。 或者，如果保持寄存器中的元素具有较高的优先级，则将新元素写入堆栈的顶部。 这保证保持寄存器始终包含具有最高优先级的元素。 因此，通过读取保持寄存器的内容来读取优先级队列保证了最高优先级元素在那里，并且可以立即访问而不进一步搜索队列。

公开(公告)号：EP0248508A2

公开(公告)日：1987-12-09

申请号：EP87302292.5

申请日：1987-03-18

申请人： INTERNATIONAL COMPUTERS LIMITED

发明人： Thompson, Roger David

IPC分类号： G06F13/36

CPC分类号： G06F13/37 ,  G06F13/376

摘要： A computer network is described, consisting of a number of computers connected by a bus. Each computer in turn becomes master, and can send messages to the other computers. When it is finished its turn as master, it passes control on to the next computer by means of a relinquish message. Each computer, when it is not master, monitors the bus for messages destined for it. If it does not detect any messages within a predetermined time interval, it enters a contention mode in which it repeatedly sends a message until either (a) it receives a response to the message in which case it becomes master or (b) it receives another message, in which case it becomes a slave. Each computer sends the contention messages at a different repetition rate, chosen such that, whatever the initial phasing of the contention messages, one message from one computer will always get through within a predetermined number of transmission attempts.

摘要翻译： 描述了一个计算机网络，由一些通过总线连接的计算机组成。 每台电脑依次成为主机，并可以向其他计算机发送消息。 当它作为主人完成轮回时，它通过放弃信息将控制权传给下一台计算机。 每个计算机，当它不是主机时，监视总线以发送给它的消息。 如果在预定时间间隔内没有检测到任何消息，则它进入竞争模式，其中它重复发送消息，直到（a）它接收到对该消息的响应，在这种情况下，该消息变为主服务器，或者（b） 消息，在这种情况下，它成为奴隶。 每个计算机以不同的重复速率发送争用消息，被选择为使得无论竞争消息的初始阶段如何，来自一台计算机的一个消息将始终在预定数量的传输尝试中通过。

公开(公告)号：EP0205467A1

公开(公告)日：1986-12-30

申请号：EP85905710

申请日：1985-11-01

申请人： MOTOROLA INC

发明人： COMROE RICHARD ALAN ,  BORRAS JAIME ANDRES ,  BROWAND WAYNE HARRY ,  RAMOS OZZIE FRANCISCO ,  KOZLOWSKI TED ANTHONY ,  MITCHELL TIMOTHY ALAN ,  EKL RANDY LEE

IPC分类号： H04L29/06 ,  G06F13/376 ,  G06F13/42 ,  H04L12/413

CPC分类号： H04L12/40013 ,  G06F13/376 ,  G06F13/4208 ,  H04L12/413

摘要： Un protocole de bus série à économie de transmission comprenant au moins un mot de huit bits, et comprenant au moins un code d'opération et un sous-argument (Figure 2). Le code d'opération et le sous-argument comprennent, respectivement, ou bien un caractère de début de message ou bien un caractère de début de réponse et, ou bien une adresse de destination du dispositif ou une adresse (Fig. 3) de source du dispositif. De plus, un dispositif de détection des erreurs est prévu comprenant un bit de parité paire. Est prévue en outre une méthode optimisée de choix de bus consistant à contrôler le bus (230) pour déterminer son état libre ou occupé et soit tenter un accès asynchrone au bus si celui-ci est libre soit tenter une nouvelle fois de façon synchrone avec priorité après détection de l'état occupé du bus, après détection d'une collision d'accès au bus, et après augmentation initiale de la puissance, synchronisée pour achèvement du message en cours. La prioritisation comprend un retard en temps constant plus un retard en temps de bits proportionnel à l'identification d'adresse du dispositif d'accès (Fig. 5). Est enfin prévue une méthode optimisée d'adressage de messages inter-dispositifs (120, 140, 150, 180, 190, 200) et d'échange de signaux de commande dans un système à bus à accès multiple, chaque dispositif possédant une adresse de source et une adresse de destination, comprenant l'adressage d'un message à une adresse de destination et l'attente que le dispositif de destination à qui on s'est adressé accuse réception par le renvoi de son adresse de source correspondante, et comprenant aussi le contrôle de bus (230) pour annoncer un événement comportant une adresse de source et remplissant une fonction en conséquence.

公开(公告)号：EP0022170B1

公开(公告)日：1983-04-13

申请号：EP80102983.6

申请日：1980-05-29

申请人： International Business Machines Corporation

发明人： Eswaran, Kapali Palaniyandi ,  Hamacher, Vincent Carl ,  Shedler, Gerald Stuart

IPC分类号： H04L11/16 ,  H04L5/00 ,  G06F15/16 ,  G06F3/04

CPC分类号： H04L12/413 ,  G06F13/376 ,  H04L12/40006

公开(公告)号：EP0051960A1

公开(公告)日：1982-05-19

申请号：EP81305108.3

申请日：1981-10-28

申请人： XEROX CORPORATION

发明人： Lam, Kai Yiu ,  Mager, George Edward

IPC分类号： G06F3/04 ,  H04L11/16

CPC分类号： H04L12/413 ,  G06F13/376

摘要： A shared line transmitter is operative to accept as a message one or more bytes of data in parallel from an input-output channel for predetermined buffering and phase encoding for transmission to a shared line except upon receipt of signal indicating that another transmitter is attempting to gain access to the shared line. It includes an output buffer operative to receive the message from the input-output channel and hold it for a predetermined period; a memory operative to receive the message from the output buffer and hold it for a predetermined period for subsequent transmission in serial form; a phase encoder operative to receive the data in serial form for conversion to a predetermined phase-encoded form for outputting to the shared line. and means for aborting the conversion upon receipt of a message-collision signal for transmitting a signal onto the shared line to abort all concurrent message transmissions, and backoff logic operative to receive the abort signal from the phase encoder to generate a random number representing the period that must elapse before the next transmission.

摘要翻译： 共享线路发射机可操作以接收来自输入 - 输出信道的一个或多个数据字节作为消息，用于预定的缓冲和相位编码以传输到共享线路，除了接收到指示另一个发射机试图获得的信号 访问共享线路。 它包括输出缓冲器，用于从输入 - 输出通道接收消息并将其保持预定的时间段; 存储器，其用于从所述输出缓冲器接收所述消息并将其保持预定的时间段以用于后续的串行传输; 用于以串行形式接收数据以转换为用于输出到共享线路的预定相位编码形式的相位编码器，以及用于在接收到用于将信号发送到共享线路上的消息冲突信号时中止该转换的装置， 中止所有并发消息传输，并且退避逻辑可操作以从相位编码器接收中止信号，以生成表示在下次发送之前必须经过的周期的随机数。

公开(公告)号：EP0022170A3

公开(公告)日：1981-04-22

申请号：EP80102983

申请日：1980-05-29

申请人： International Business Machines Corporation

发明人： Eswaran, Kapali Palaniyandi ,  Hamacher, Vincent Carl ,  Shedler, Gerald Stuart

IPC分类号： H04L11/16 ,  H04L05/00 ,  G06F15/16 ,  G06F03/04

CPC分类号： H04L12/413 ,  G06F13/376 ,  H04L12/40006

摘要： Asynchronous, collision-free communication of data packets is provided on a local shared bus network interconnecting a plurality of N ordered transceiving ports (1,2,3....,J,...N). The bus network includes a data bus (20) having a propagation delay time T and a control line (26) having a propagation delay from port J to port N of R(J), each port J including means (40) for ascertaining the presence of a data packet on said data bus at said port J, and being adapted to send and receive on said data bus variable length data packets. Each port J upon having a packet available for transmission executes the steps of placing a signal S(J) on said control line (26) to communicate to ports J + 1, J +2,...,N an intention to transmit a packet, delaying transmission for the time interval R(J) + T, ascertaining that no signal indicating an intention to transmit is being received at port J from any of ports 1,2,...,J- 1 , and that said data bus (20) at port J is unoccupied, transmitting the packet and terminating signal S(J). Prior to placing the signal S(J) on the control line (26), the port J ascertains that the data bus (20) is unoccupied for a time period 2T.

公开(公告)号：EP0004376A2

公开(公告)日：1979-10-03

申请号：EP79100859.2

申请日：1979-03-21

申请人： THE MITRE CORPORATION

发明人： Hopkins, Gregory T. ,  Wagner, Paul E.

IPC分类号： H04L11/16

CPC分类号： G06F13/376 ,  H04L12/40032 ,  H04L12/413

摘要： A multiple access digital communications system comprises a plurality of remotely located terminals coupled to a communications bus including a pair of oppositely directed, unidirectional signal paths (10, 12) and a unidirectional path coupler (14) for transferring signals from the inbound path (10) to the outbound path (12).
To send a message from one terminal to another desired terminal, a corresponding bus interface unit (20A) coupled to both the inbound and outbound paths (10, 12) is adapted to perform an rf. carrier sensing operation to determine as to whether or not any other subscriber is transmitting on the inbound path (10). If no carrier is detected, the bus interface unit (20A) confirms this determination by first beginning to transmit a message packet and then monitoring the outbound path (12) during a collision window. If the transmitted message is received intact within this collision window, the bus interface unit (20A) may transmit any remaining portion of its message packet on the inbound path (10).

摘要翻译： 多址数字通信系统包括耦合到通信总线的多个远程定位终端，该通信总线包括一对相反方向的单向信号路径（10,12）和用于从入站路径（10,12）传送信号的单向路径耦合器（14） ）到出站路径（12）。 为了将消息从一个终端发送到另一个期望的终端，耦合到入站和出站路径（10,12）的对应总线接口单元（20A）适于执行rf。 载波感测操作，以确定任何其他用户是否在入站路径（10）上进行发送。 如果没有检测到载波，则总线接口单元（20A）首先确认该确定，以发送消息分组，然后在冲突窗口期间监视出站路径（12）。 如果发送的消息在该冲突窗口内被完整地接收，则总线接口单元（20A）可以在入站路径（10）上发送其消息分组的剩余部分。

公开(公告)号：EP3103021A1

公开(公告)日：2016-12-14

申请号：EP15706327.2

申请日：2015-02-06

申请人： Ascensia Diabetes Care Holdings AG

发明人： DIONISIO, Christopher ,  SWANZEY, Todd T. ,  STEFKOVIC,Gregory R.

IPC分类号： G06F13/376 ,  G06F13/42

CPC分类号： G06F13/364 ,  G06F13/376 ,  G06F13/404 ,  G06F13/4282 ,  G06F2213/0016

摘要： Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial computer bus; a first master coupled to the bus; a second master coupled to the bus; a slave device coupled to the bus; a first I/O line from the first master going to the second master and the slave device; and a second I/O line from the second master going to the first master and the slave device. A bus arbitration protocol for arbitrating use of the bus restricts the masters to a single transaction each time either master becomes a bus master, and the masters are each adapted to use the I/O lines to signal to each other not to become a bus master. Numerous other aspects are disclosed.

公开(公告)号：EP2490001B1

公开(公告)日：2016-12-14

申请号：EP09850379.0

申请日：2009-10-14

申请人： Tohoku University ,  Kabushiki Kaisha Toyota Chuo Kenkyusho ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： MUROYAMA, Masanori ,  ESASHI, Masayoshi ,  TANAKA, Shuji ,  MATSUZAKI, Sakae ,  MAKIHATA, Mitsutoshi ,  NONOMURA, Yutaka ,  FUJIYOSHI, Motohiro ,  NAKAYAMA, Takahiro ,  YAMAGUCHI, Ui ,  YAMADA, Hitoshi

IPC分类号： G01L1/00 ,  G01L5/00 ,  G06F13/362 ,  H04L12/413

CPC分类号： H04L12/40032 ,  G01L1/142 ,  G01L1/146 ,  G01L5/228 ,  G06F13/376 ,  H04L12/40013

摘要： A touch sensor system 100 includes buses 110, a plurality of touch sensor devices 200 disposed on the buses 110, and an information integrating device 140 that is connected to all the buses 110 and integrates information from the touch sensor device 200. The touch sensor device 200 includes a sensor unit and a signal processing unit that transmits a sensor data signal generated by processing an analog sensor signal to the information integrating device through the bus. The signal processing unit includes a digital converting unit, a threshold evaluating unit that gives a start permission of the signal process when a sensor value exceeds a preset threshold, an ID adding unit that adds a transmitter identification number to the sensor signal, and a data transmitting unit that outputs the sensor data signal to a signal line of the bus. Fast responses are made possible without increasing the amount of data and host processing load while including many touch sensor elements.