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147 条记录 (耗时 0.015 秒)

    Complementary output circuit for logic circuit
    21.
    发明公开
    Complementary output circuit for logic circuit 失效
    Komplementärausgangsschaltungfüreine logische Schaltung。

    公开(公告)号：EP0341740A2

    公开(公告)日：1989-11-15

    申请号：EP89108612.6

    申请日：1989-05-12

    申请人： NEC CORPORATION

    发明人： Aoki, Yasushi

    IPC分类号： H03K19/017 ,  H03K19/0175

    CPC分类号： H03K19/215 ,  H03K19/01707

    摘要： An output circuit for a high speed and low power logic circuit is disclosed. The logic circuit (7) performs a logic operation on a plurality of input data signals supplied thereto and produces true and complementary intermediate output signals (P, P ), the logic high level of the intermediate output signal being lower than a first power voltage (V DD ) and the logic low level thereof being substantially equal to a second power voltage (GND). The output circuit (8) includes a P-channel MOS transistor (MP11, MP12) having a gate supplied with the complementary intermediate output signal ( P ,P), a source connected to a power voltage supplied with the first power voltage and a drain connected to an output terminal, and an N-channel MOS transistor (MN11, MN12) having a gate connected to the power terminal, a source supplied with the true intermediate output signal (P, P ) and a drain connected to the output terminal, and thus produces at the output terminal an output signal having a substantial logic amplitude between the first (V DD ) and second power voltages (V GND ).

    摘要翻译： 公开了一种用于高速和低功率逻辑电路的输出电路。 逻辑电路（7）对提供给其的多个输入数据信号执行逻辑运算，并产生真实和互补的中间输出信号（P，P），中间输出信号的逻辑高电平低于第一电源电压 VDD），其逻辑低电平基本上等于第二电源电压（GND）。 输出电路（8）包括具有提供有互补中间输出信号（P，P）的栅极的P沟道MOS晶体管（MP11，MP12），连接到提供有第一电源电压的电源电压的源极和漏极 连接到输出端子和具有连接到电源端子的栅极的N沟道MOS晶体管（MN11，MN12），提供有真实中间输出信号（P，P）的源极和连接到输出端子的漏极， 并且因此在输出端产生具有在第一（VDD）和第二电源电压（VGND）之间的实质逻辑幅度的输出信号。

    High speed logic circuit
    22.
    发明公开
    High speed logic circuit 失效
    Logische Schaltung hoher Geschwindigkeit。

    公开(公告)号：EP0337078A2

    公开(公告)日：1989-10-18

    申请号：EP89102647.8

    申请日：1989-02-16

    申请人： HONEYWELL INC.

    发明人： Fulkerson, David E.

    IPC分类号： H03K19/017

    CPC分类号： H03K19/0013 ,  H03K19/01707

    摘要： An improved FET capacitance driver logic circuit has an inverter feedback stage (22) connected from the output to the input of an output FET (23) to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.

    摘要翻译： 改进的FET电容驱动器逻辑电路具有从输出端连接到输出FET（23）的输入的反相器反馈级（22），以允许输出FET具有大的电容充电电流浪涌，之后是导通的减小的导通。

    Multibase bi-CMOS logic circuit family
    23.
    发明公开
    Multibase bi-CMOS logic circuit family 失效
    Logische Schaltkreisfamilie von Multibasis-bi-CMOS。

    公开(公告)号：EP0318624A1

    公开(公告)日：1989-06-07

    申请号：EP87480020.4

    申请日：1987-12-01

    申请人： International Business Machines Corporation

    发明人： Boudon, Gérard ,  Ong, Ieng ,  Mollier, Pierre

    IPC分类号： H03K19/094

    CPC分类号： H03K19/013 ,  H03K19/01707 ,  H03K19/09448 ,  H03K19/215

    摘要： A multi base 2 input Bi-CMOS NAND circuit (30) is provided wherein an output node OUT connected to an output terminal (33) is coupled between pull up (31) and pull down (32) blocks. According to the present invention, the pull up block (31) is comprised of 2 identical basic cells, each comprised of a CMOS inverter (C31, C32) driving a NPN pull up transistor (T31, T32) mounted as an emitter follower. Logic signals (A31, A32) are applied on the inputs of the inverters (C31, C32), and the inverted signal ( A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All emitters are tied altogether to perform an OR function and are connected to said output terminal (33).
    As standard, the pull down block (32) includes a logic stack (34) is comprised of 2 FETS (F31, F32) serially connected between said output node OUT and a discharge device such as a feedback NFET (Z), the gate of which is connected to said output node OUT. These 2 FETS are driving a NPN pull down transistor (T), the collector of which is also connected to the output node OUT.

    摘要翻译： 提供了多基极2输入Bi-CMOS NAND电路（30），其中连接到输出端子（33）的输出节点OUT耦合在上拉（31）和下拉（32）块之间。 根据本发明，上拉块（31）由两个相同的基本单元组成，每个单元由驱动安装为发射极跟随器的NPN上拉晶体管（T31，T32）的CMOS反相器（C31，C32）组成。 在反相器（C31，C32）的输入端施加逻辑信号（A31，A32），反相信号（A31，A32）在与发射极输出对应的射极跟随器的发射极处可用。 所有发射器一起被连接以执行OR功能并且连接到所述输出端子（33）。 作为标准，下拉块（32）包括逻辑堆叠（34），其包括串联连接在所述输出节点OUT和诸如反馈NFET（Z）的放电装置之间的2个FETS（F31，F32），栅极 其连接到所述输出节点OUT。 这两个FETS驱动NPN下拉晶体管（T），其集电极也连接到输出节点OUT。

    Integrated driving stage for a fet logic circuit
    24.
    发明公开
    Integrated driving stage for a fet logic circuit 失效
    Integrierte Steuerungsstufefürlogische FET-Schaltung。

    公开(公告)号：EP0242523A2

    公开(公告)日：1987-10-28

    申请号：EP87102195.2

    申请日：1987-02-17

    申请人： International Business Machines Corporation

    发明人： Anderson, Carl John

    IPC分类号： H03K19/094

    CPC分类号： H03K19/09443 ,  H03K19/01707

    摘要： Digital logic driving stage circuitry is provided connected between ground (11) and a single voltage (V) with an enhancement mode type field effect transistor (2)and a depletion mode type field effect transistor (9)connected source to drain in series between the single voltage and ground. The gate (8) of the enhancement mode type field effect transistor (2) is the input of the logic signal and the gate (13) of the depletion mode type field effect transistor (9) is connected to ground (11), with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input (15, 16, 17), depletion mode load (30) circuitry stage and an enhancement mode input grounded source follower load driving stage (2, 9).

    摘要翻译： 数字逻辑驱动级电路通过增强型场效应晶体管（2）和耗尽型场效应晶体管（9）连接在接地（11）与单电压（V）之间，其中源极与漏极串接在 单电压和接地。 增强型场效应晶体管（2）的栅极（8）是逻辑信号的输入，耗尽型场效应晶体管（9）的栅极（13）与地（11）连接，与 在晶体管之间的连接处输出。 数字逻辑电路系列具有由增强模式逻辑输入（15,16,17），耗尽模式负载（30）电路级和增强模式输入接地源极跟随器负载驱动级（2,9）构成的电路单元 ）。

    Current switching logic circuit generating matched rise and fall times
    26.
    发明公开
    Current switching logic circuit generating matched rise and fall times 审中-公开
    电流开关逻辑电路产生匹配的上升和下降时间

    公开(公告)号：EP1320194A1

    公开(公告)日：2003-06-18

    申请号：EP03005785.5

    申请日：2001-07-04

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

    发明人： Asano, Hiroaki ,  Saito, Mitsuru

    IPC分类号： H03K19/017

    CPC分类号： H03K19/00323 ,  H03K19/01707 ,  H03K19/09432

    摘要： A logic circuit for receiving a plurality of input differential signal pairs expressing respective logic inputs and for sequentially performing a plurality of logic operations on said logic inputs in successive logic stages, the logic circuit comprising
       a plurality of current switching sections corresponding to respective ones of said logic stages, with each of said current switching sections performing predetermined logic processing on a plurality of differential control signal pairs having a plurality of level ranges,
       a control signal generating section for converting each pair of said plurality of input differential signal pairs to a plurality of corresponding differential signal pairs having a plurality of level ranges, and supplying said corresponding differential signal pairs to a current switching section of a first logic stage, as respective differential control signal pairs,
       a plurality of inter-stage output signal generating sections each adapted to convert a differential signal pair produced by a preceding one of said current switching sections to produce a corresponding plurality of differential control signal pairs having respectively different level ranges and supplying said differential control signal pairs to a succeeding one of said current switching sections, and
       an output signal generating circuit for converting a differential signal pair produced by a current switching section of a final logic stage to an output differential signal pair.

    摘要翻译： 一种逻辑电路，用于接收表示各自逻辑输入的多个输入差分信号对，并且用于在连续逻辑级中的所述逻辑输入上顺序地执行多个逻辑操作，所述逻辑电路包括多个电流切换部分，所述多个电流切换部分对应于所述各个所述 逻辑级，每个所述电流切换部分对具有多个电平范围的多个差分控制信号对执行预定的逻辑处理;控制信号产生部分，用于将所述多个输入差分信号对中的每一对变换成多个 对应的具有多个电平范围的差分信号对，并将所述对应的差分信号对提供给第一逻辑级的电流切换部分作为各自的差分控制信号对;多个级间输出信号生成部分， 转换由前述一个电流开关部分产生的差分信号对，以产生具有各自不同电平范围的相应的多个差分控制信号对，并将所述差分控制信号对提供给后续的所述电流开关部分， 信号发生电路，用于将由最终逻辑级的电流切换部分产生的差分信号对转换为输出差分信号对。

    A low voltage differential to single-ended converter
    27.
    发明公开
    A low voltage differential to single-ended converter 有权
    Niederspannungskonverter mit Differenzeingang und einem einzigen Ausgang

    公开(公告)号：EP1251640A2

    公开(公告)日：2002-10-23

    申请号：EP02252681.8

    申请日：2002-04-16

    申请人： Broadcom Corporation

    发明人： Kocaman, Namik

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018514 ,  H03K19/01707 ,  H03K19/09429

    摘要： Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.

    摘要翻译： 用于将差分逻辑信号转换为单端逻辑信号的方法和电路消除了较慢的PMOS晶体管并加速了转换过程。 在具体实施例中，在例如电流控制的互补金属氧化物半导体（C3MOS）逻辑中使用的类型的差分逻辑信号被转换为单端轨至轨CMOS逻辑电平，使用具有 电阻作为负载器件和NMOS电流源晶体管，提供动态调整的尾电流。

    Circuit for dynamic switching of a buffer threshold
    30.
    发明公开
    Circuit for dynamic switching of a buffer threshold 有权
    Schaltung zur dynamischen Umschaltung einer Pufferschwelle

    公开(公告)号：EP1041719A1

    公开(公告)日：2000-10-04

    申请号：EP00650006.0

    申请日：2000-01-31

    申请人： Fairchild Semiconductor Corporation

    发明人： Morrill, David P.

    IPC分类号： H03K19/017 ,  H03K19/00

    CPC分类号： H03K19/01707 ,  H03K19/0027

    摘要： A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters (IV1,IV2) designed with different skewed threshold potential characteristics. The outputs of the skewed inverters (IV1,IV2) are directed to a logic circuit (30) designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices (40,50) coupled to the respective inverters. Only one of the passgate devices (40,50) is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch (60) is preferably connected between the logic circuit (30) and the two passgate devices (40,50) to maintain the states of the inverters (IV1,IV2) and the logic circuit (30). The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.

    摘要翻译： 一种用于提供动态阈值控制的缓冲电路。 缓冲电路包括设计成具有不同偏斜阈值电位特性的一对输入反相器（IV1，IV2）。 偏斜反相器（IV1，IV2）的输出被引导到逻辑电路（30），逻辑电路（30）被设计成选择从两个反相器接收的更快或更慢的信号以传输到耦合到各个反相器的通道装置（40,50） 。 只有一个通道装置（40,50）能够确保来自两个反相器的输出信号中只有一个通过缓冲器传播。 闩锁（60）优选地连接在逻辑电路（30）和两个通过门装置（40,50）之间，以维持反相器（IV1，IV2）和逻辑电路（30）的状态。 电路可以被设计为定义将发生切换的阈值电位，以便减少传播延迟或者根据需要增加延迟。 因此，使用电路可以以最小的对信号噪声的影响来增加传输速率。