公开(公告)号：EP4009366A1

公开(公告)日：2022-06-08

申请号：EP21210343.6

申请日：2021-11-25

申请人： MACOM Technology Solutions Holdings, Inc.

发明人： PATEL, Prity Kirit

IPC分类号： H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L23/00 ,  H01L23/522

摘要： New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are presented. In one example, an integrated device includes a capacitor network and one or more power devices. The capacitor network includes a bond pad and metal-insulator-metal (MIM) capacitors. The capacitors include a first metal layer, a second metal layer, an insulator layer between the first and second metal layers, and one or more through-substate vias. The first metal layer is coupled to the bond pad, and the second metal layer is coupled to a ground plane on a bottom side of the substrate by the vias. A number of capacitors can be arranged around the bond pad in the capacitor network for a tailored capacitance. A matching network in the integrated device can incorporate the capacitor network to reduce loss, provide better harmonic termination, and achieve better phase alignment for the power devices.

公开(公告)号：EP3471140B1

公开(公告)日：2022-05-18

申请号：EP17306368.6

申请日：2017-10-11

发明人： Robert, Sebastien ,  Le Moal, Guy

IPC分类号： H01L23/522 ,  H03H7/42 ,  H01P5/10 ,  H01F19/04 ,  H01L23/64 ,  H01F17/00 ,  H01F27/28 ,  H01L23/66 ,  H01L49/02 ,  H03H7/25

公开(公告)号：EP3987641A1

公开(公告)日：2022-04-27

申请号：EP20730841.2

申请日：2020-05-15

申请人： QUALCOMM INCORPORATED

发明人： YU, Chengyue ,  LOW, Zhen Ning ,  GUO, Guoyong ,  CHEN, Jiwei

IPC分类号： H02M3/156 ,  H01L23/64 ,  H05K1/02

公开(公告)号：EP3973569A1

公开(公告)日：2022-03-30

申请号：EP20729817.5

申请日：2020-05-19

申请人： PragmatIC Printing Ltd

发明人： COBB, Brian ,  PRICE, Richard

IPC分类号： H01L23/00 ,  H01L23/64 ,  H01L23/552

公开(公告)号：EP3910670A1

公开(公告)日：2021-11-17

申请号：EP20795473.6

申请日：2020-02-22

申请人： Changxin Memory Technologies, Inc.

发明人： DAI, Chi-Wei

IPC分类号： H01L23/64 ,  H01L21/027

摘要： Disclosed are capacitors (1211, 1212), a forming method therefor, and a DRAM unit. The forming method for the capacitors (1211, 1212) comprises: providing a substrate (100), wherein an electrical contact part (101) is formed in the substrate (100); forming a dielectric layer (110) on the surface of the substrate (100), the dielectric layer (110) comprising: support layers (102, 104, 106) and sacrificial layers (103, 105) that are alternatingly stacked; forming at least two capacitor holes (601) that penetrate the sacrificial layers (103, 105) and the support layers (102, 104, 106) and expose the same electrical contact part (101); forming a lower electrode layer (701) that covers the inner wall of the capacitor holes (601), the lower electrode layer (701) being connected to the electrical contact part (101); removing the sacrificial layers (103, 105); successively forming a capacitor dielectric layer (1101) and an upper electrode layer (1102) at inner and outer surfaces of the lower electrode layer (701) and at surfaces of the support layers (102, 104, 106). The described method may improve the capacitance value per unit area of the capacitors (1211, 1212).

公开(公告)号：EP3907760A1

公开(公告)日：2021-11-10

申请号：EP20173688.1

申请日：2020-05-08

申请人： Infineon Technologies Austria AG

发明人： NOEBAUER, Gerhard ,  YUFEREV, Sergey

IPC分类号： H01L25/07 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L23/64 ,  H01L23/538

摘要： In an embodiment a semiconductor module comprises a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a VIN package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further comprises a first capacitor pad coupled to ground potential and a second capacitor pad coupled to VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

公开(公告)号：EP3893275A1

公开(公告)日：2021-10-13

申请号：EP20823455.9

申请日：2020-06-12

申请人： Huawei Technologies Co., Ltd.

发明人： XIANG, Zhiqiang

IPC分类号： H01L23/495 ,  H01L23/64 ,  H01L25/16

摘要： This application provides a packaged module and a metal plate. The packaged module may include a bearing structure, at least one metal strip, a circuit element, and a magnetic material. Specifically, a first surface of the bearing structure may bear the circuit element; two ends of each of the at least one metal strip may be coupled to the bearing structure, and a part of each metal strip other than the two ends is spaced apart from the bearing structure; and the magnetic material may cover a surface of a winding functional region of the at least one metal strip, where the winding functional region may be a part or all of the metal strip to which the winding functional region belongs. The foregoing solution helps simplify a packaging process and reduce losses and manufacturing costs of the packaged module.

公开(公告)号：EP3123508B1

公开(公告)日：2021-09-29

申请号：EP15715112.7

申请日：2015-03-27

发明人： FAZELPOUR, Siamak ,  PAYNTER, Charles David ,  LANE, Ryan David

IPC分类号： H01L23/498 ,  H01F17/00 ,  H01L23/64 ,  H01L49/02

公开(公告)号：EP3859779A1

公开(公告)日：2021-08-04

申请号：EP21152192.7

申请日：2021-01-18

申请人： NXP USA, Inc.

发明人： Schultz, Joseph Gerard ,  Kim, Kevin

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L23/64

摘要： Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

公开(公告)号：EP3855501A1

公开(公告)日：2021-07-28

申请号：EP18901811.2

申请日：2018-10-08

申请人： Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

发明人： XIAO, Hui ,  IM, Jangsoon

IPC分类号： H01L27/32 ,  H01L23/64

摘要： The present application proposes a display panel, a manufacturing method for the display panel, and a display module. The display panel includes an array substrate. The array substrate includes a substrate and a thin film transistor and a storage capacitor on the substrate. The storage capacitor includes a first electrode on the substrate, a first insulating layer on the first electrode, a second electrode on the first insulating layer, a second insulating layer on the second electrode, and a third electrode on the second insulating layer. An orthogonal projection of the second electrode on the second insulating layer is on the second insulating layer.