ELECTRONIC DEVICE AND ITS METHOD OF MANUFACTURE
    5.
    发明公开
    ELECTRONIC DEVICE AND ITS METHOD OF MANUFACTURE 审中-公开
    VERFAHREN ZU IHRER HERSTELLUNG的ELEKTRONISCHE VORRICHTUNG

    公开(公告)号:EP2691985A1

    公开(公告)日:2014-02-05

    申请号:EP12719435.5

    申请日:2012-03-30

    IPC分类号: H01L29/786 H01L29/66

    摘要: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.

    摘要翻译: 一种制造电子器件的方法包括:提供包括第一部分,第二部分和第三部分的半导体材料层,第三部分将第一部分连接到第二部分,并提供半导体通道,用于在 第一和第二部分; 提供相对于所述第三部分布置的栅极端子,使得可以向栅极端子施加电压以控制所述沟道的电导率; 以及当没有电压施加到所述栅极端子时,处理所述第一部分和所述第二部分中的至少一个,使得具有大于所述沟道的电导率的导电性。 在某些实施例中,处理包括将第一和第二部分中的至少一个暴露于电磁辐射。 第一和第二部分可以被激光退火以增加它们的电导率。

    TRANSISTOR AND ITS METHOD OF MANUFACTURE
    8.
    发明公开
    TRANSISTOR AND ITS METHOD OF MANUFACTURE 审中-公开
    VERFAHREN ZU DESSEN HERSTELLUNG的TRANSISTOR

    公开(公告)号:EP2724373A2

    公开(公告)日:2014-04-30

    申请号:EP12730616.5

    申请日:2012-06-22

    IPC分类号: H01L29/66 H01L27/12

    摘要: A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.

    摘要翻译: 一种制造晶体管的方法,包括:提供衬底,由衬底支撑的半导体材料的区域和由半导体材料区域支撑的导电材料区域; 在所述区域上形成至少一层抗蚀剂材料,以在所述区域上形成抗蚀剂材料的覆盖层; 在抗蚀剂材料的覆盖物的表面上形成凹陷,所述凹陷在导电材料区域的第一部分上延伸,所述第一部分将导电区域的第二部分与导电区域的第三部分分开; 去除位于所述凹陷下方的抗蚀剂材料,以形成通过所述覆盖物的窗口,暴露所述导电区域的所述第一部分; 去除所述第一部分以暴露所述半导体材料区域的连接部分,所述连接部分将所述第二部分连接到所述导电区域的第三部分; 在半导体材料的区域的暴露部分上形成介电材料层; 以及沉积导电材料以在所述介电材料层上形成导电材料层,所述介电材料层将所述导电材料层与所述导电区域的第二和第三部分电隔离。

    ELECTRONIC CIRCUITS INCLUDING PLANAR ELECTRONIC DEVICES
    9.
    发明公开
    ELECTRONIC CIRCUITS INCLUDING PLANAR ELECTRONIC DEVICES 有权
    与平面电子部件的集成电路的生产互连的方法

    公开(公告)号:EP2504856A1

    公开(公告)日:2012-10-03

    申请号:EP10803126.1

    申请日:2010-11-23

    IPC分类号: H01L21/768

    摘要: A method comprises: forming a structure comprising a layer of active material (1), a first conductive track (2) separated from the layer of active material by a layer of insulative material ( 3 ), the layer of active material having a plurality of insulative features (110) formed therein, the insulative features defining at least a first substantially planar electronic device comprising at least a respective first terminal (11) and a respective second terminal (12), and at least a portion of said first conductive track overlapping one of the first and second terminals; forming a first hole (4) extending through the layer of insulative material and connecting an overlapping portion of the first conductive track to one of the first and second terminals; and filling said first hole at least partly with electrically conductive material.