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    A 3D SEMICONDUCTOR DEVICE AND SYSTEM
    25.
    发明公开
    A 3D SEMICONDUCTOR DEVICE AND SYSTEM 审中-公开

    公开(公告)号：EP3460845A1

    公开(公告)日：2019-03-27

    申请号：EP18195847.1

    申请日：2011-06-28

    申请人： Monolithic 3D Inc.

    发明人： Or-Bach, Zvi ,  Sekar, Deepak C. ,  Cronquist, Brian

    IPC分类号： H01L27/06 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11529

    摘要： A 3D semiconductor device, the device including: a plurality of first transistors, overlaid by a plurality of second memory cells, overlaid by a plurality of third memory cells, overlaid by a plurality of fourth memory cells, where the second memory cells, the third memory cells and the fourth memory cells are self-aligned, having been processed following the same lithography step, and where a periphery circuit includes at least one of the first transistors and the periphery circuit controls at least one of the second memory cells, at least one of the third memory cells and at least one of the fourth memory cells, and where at least one of the second memory cells includes second transistors, at least one of the second transistors is a junction-less transistor.

    Semiconductor device including nonvolatile memory
    26.
    发明公开
    Semiconductor device including nonvolatile memory 审中-公开
    半导体器件包括非易失性存储器

    公开(公告)号：EP2346076A3

    公开(公告)日：2017-05-03

    申请号：EP11162973.9

    申请日：2004-01-16

    申请人： Kabushiki Kaisha Toshiba

    发明人： Takebuchi, Masataka ,  Arai, Fumitaka

    IPC分类号： H01L27/105 ,  H01L21/8238 ,  H01L27/11546 ,  H01L27/11539 ,  H01L27/11536 ,  H01L27/11529 ,  H01L21/8246 ,  H01L27/112

    CPC分类号： H01L21/823857 ,  H01L27/112 ,  H01L27/1122 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11546

    摘要： A semiconductor device, comprising: a semiconductor substrate (30); a nonvolatile memory cell (47) including a first MOS transistor having a first gate formed on the semiconductor substrate, the first gate being a layered gate structure having a first gate insulating film (32), a first gate electrode film (33), a second gate insulating film (34), a second gate electrode film (44), and a source and a drain (46) formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate; and a logic circuit including a plurality of second MOS transistors, each of the second MOS transistors having a second gate formed on the semiconductor substrate, the second gate being a gate structure having a third gate insulating film and a second gate electrode film, and a source and a drain formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the second gate, the plurality of second MOS transistors including at least a second MOS transistor having a third gate insulating film of a first thickness (38), a second MOS transistor having a third gate insulating film of a second thickness (40) and a second MOS transistor having a third gate insulating film of a third thickness (42); wherein the first thickness is thicker than the second thickness and the second thickness is thicker than the third thickness, and a thickness of the second gate insulating film is thicker than the second thickness and thinner than the first thickness.

    摘要翻译： 一种半导体器件，包括：半导体衬底（30）; 包括第一MOS晶体管的非易失性存储单元（47），所述第一MOS晶体管具有形成在所述半导体衬底上的第一栅极，所述第一栅极是具有第一栅极绝缘膜（32）的分层栅极结构，第一栅电极膜（33）， 第二栅极绝缘膜（34），第二栅极电极膜（44）以及在半导体衬底中形成的源极和漏极（46），以将半导体衬底的表面区域置于第一栅极下方; 以及包括多个第二MOS晶体管的逻辑电路，每个第二MOS晶体管具有形成在半导体衬底上的第二栅极，第二栅极是具有第三栅极绝缘膜和第二栅极电极膜的栅极结构，以及 源极和漏极，形成在所述半导体衬底中以将所述半导体衬底的表面区域置于所述第二栅极下方，所述多个第二MOS晶体管至少包括具有第一厚度（38）的第三栅极绝缘膜的第二MOS晶体管， 第二MOS晶体管，具有第二厚度的第三栅极绝缘膜和具有第三厚度的第三栅极绝缘膜的第二MOS晶体管; 其中，所述第一厚度比所述第二厚度厚且所述第二厚度比所述第三厚度厚，并且所述第二栅极绝缘膜的厚度比所述第二厚度厚且比所述第一厚度薄。