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178 条记录 (耗时 0.016 秒)

    High speed processor
    32.
    发明公开
    High speed processor 失效
    Hochgeschwindigkeitsprozessor。

    公开(公告)号：EP0157306A2

    公开(公告)日：1985-10-09

    申请号：EP85103348.0

    申请日：1985-03-22

    申请人： International Business Machines Corporation

    发明人： Ngai, Chuck Hong ,  Wassel, Edward Richard

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3877

    摘要： A high speed processor (12) is disclosed for use in conjunction with a main processor (10) of a computer system. In the computer system, one program is being executed. The high speed processor executes certain selected instructions of the one program which are designated «more frequently executed" than the remaining instructions of the one program. The main processor executes the remaining instructions of the one program when the high speed processor is not executing the selected instructions. In addition, the high speed processor executes the selected instructions more rapidly than would be the case if the main processor were to execute the selected instructions. The high speed processor executes the selected instructions more rapidly due to the fact that it operates in an «overlap execution mode... In this overlap mode, the high speed processor is preparing the next instruction for execution simultaneously with the execution of the current instruction. However, an address compare circuit (12c4) disposed within the high speed processor ensures that the execution of the current instruction is completed prior to the commencement of the execution of the next instruction. In addition, a special retry buffer (12c5) is provided in the event the execution of the instruction should be repeated. As a result of the utilization of the high speed processor in conjunction with the main processor for the execution of the instructions of one program, the instruction processing time is decreased by a factor of approximately forty (40) percent. Therefore, the performance of the computer system has been optimized.

    摘要翻译： 公开了与计算机系统的主处理器（10）一起使用的高速处理器（12）。 在计算机系统中，正在执行一个程序。 高速处理器执行比一个程序的剩余指令更频繁执行的一个程序的某些所选择的指令。 当高速处理器未执行所选择的指令时，主处理器执行一个程序的剩余指令。 此外，高速处理器比主处理器要执行所选择的指令的情况更快地执行所选择的指令。 高速处理器由于其以“重叠执行模式”运行的事实，更快地执行所选择的指令。 在这种重叠模式中，高速处理器正在准备下一条指令，以执行当前指令。 然而，设置在高速处理器内的地址比较电路（12c4）确保当前指令的执行在下一个指令的执行开始之前完成。 另外，在重复执行指令的情况下，提供特殊的重试缓冲器（12c5）。 作为与主处理器一起利用高速处理器以执行一个程序的指令的结果，指令处理时间减少了大约四十（40）个百分比。 因此，计算机系统的性能得到了优化。

    A method for making logic circuits
    33.
    发明公开
    A method for making logic circuits 失效
    Verfahren zur Bildung logischer Schaltungen。

    公开(公告)号：EP0142766A2

    公开(公告)日：1985-05-29

    申请号：EP84113322.6

    申请日：1984-11-06

    申请人： International Business Machines Corporation

    发明人： Griffin, William Robert ,  Heller, Lawrence Griffith

    IPC分类号： H03K19/173 ,  H03K19/094

    CPC分类号： H03K19/0948 ,  H01L27/112

    摘要： A method is provided for reducing an arbitrary Boolean logic expression to static CMOS circuits by the use of a general matrix (10 and 12) of P channel devices and N channel devices which are interconnected in accordance with the terms of Boolean logic expressions derived from a truth table. More specifically, from a Boolean expression a sum-of-products expression giving the 1 binary data outputs of a truth table having a 0 input is found. This is accomplished by complementing, or barring, the literals which are a binary 1 when the output is 1 and leaving true or unbarred the literals that are a binary 0. Then each input (A-D; A-D) of a given product term is applied to the control gate of a P channel device, which devices are connected in series with one end tied to a source of potential (V H ) and the other end of the series circuit connected to an output terminal (Q). Each product term is arranged in parallel with other channel device series circuits to form one half of a complete logic matrix (10). Similarly, for the other halfofthe matrix (12), a sum-of-products expression giving the binary 0 outputs of a truth table having a binary 1 for an input is found. Each input of a given product term is applied to the control gate of an N channel device, which devices are connected in series with one end tied to a potential reference point, such as ground, and the other end of the series circuit is connected to the output terminal. Each product term is arranged in parallel with other N channel device series circuits.

    摘要翻译： 提供了一种通过使用P通道器件和N沟道器件的通用矩阵（10和12）将静态CMOS电路的任意布尔逻辑表达式减少的方法，该通道器件和N沟道器件根据从 真相表。 更具体地，从布尔表达式中，找到给出具有0输入的真值表的1个二进制数据输出的乘积和表达式表达式。 这是通过补充或限制当输出为1并且将真实或未标记为二进制0的字面值作为二进制1的文字时实现的。然后将给定产品项的每个输入（AD; AD）应用于 P沟道器件的控制栅极，这些器件与连接到电位源（VH）的一端串联连接，而串联电路的另一端连接到输出端（Q）。 每个产品术语与其他P通道器件串联电路并联布置以形成完整逻辑矩阵（10）的一半。 类似地，对于矩阵（12）的另一半，找到给出具有用于输入的二进制1的真值表的二进制0输出的积和表达式。 给定产品项的每个输入被施加到N沟道器件的控制栅极，这些器件与连接到电位参考点（例如地）的一端串联连接，并且串联电路的另一端连接到 输出端子。 每个产品术语与其他N通道器件串联电路并联布置。

    Integrated semiconductor memory
    34.
    发明公开
    Integrated semiconductor memory 失效
    集成半导体存储器。

    公开(公告)号：EP0128273A2

    公开(公告)日：1984-12-19

    申请号：EP84102895.4

    申请日：1984-03-16

    申请人： International Business Machines Corporation

    发明人： Scheuerlein, Roy Edwin

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4097

    摘要： A memory array is provided which includes a common sense line (22) to which is connected a first storage capacitor (12) through first switching means (14) and a second storage capacitor (18) through second switching means (20), with a common word line (24) connected to the control electrodes of the first and second switching means (14, 20), a first bit line (26) connected to a plate of the first storage capacitor and a second bit line (28) connected to a plate of the second storage capacitor. Data is stored into or read from the first storage capacitor (12) by selecting the common word line and the first bit line and data is stored into and read from the second storage capacitor (18) by selecting the common word line and the second bit line, with the data from both storage capacitors being detected on the common sense line (22).

    Priority system for channel subsystem
    36.
    发明公开
    Priority system for channel subsystem 失效
    Kanalsubsystem系统的优先系统。

    公开(公告)号：EP0118670A2

    公开(公告)日：1984-09-19

    申请号：EP84100448.4

    申请日：1984-01-17

    申请人： International Business Machines Corporation

    发明人： Capowski, Robert Stanley ,  Zimmerman, Terrence Keith

    IPC分类号： G06F13/18 ,  G06F13/20

    CPC分类号： G06F13/20 ,  G06F13/18

    摘要： A priority circuit handles requests by three components of a data processing system for access to several resources of the system that can be accessed one at a time on each operating cycle of the system. A logic circuit receives requests by the requesters (30-32) and grants access (64-66) to one requester on a priority basis. The logic circuit has means (39, 62, 63) for establishing a particular priority sequence, and the priority circuit includes means (69,72,73) for stepping the logic circuit through a cycle of different priority sequences. In a repeating cycle of these steps, each requester is given the highest priority at least once. The stepping means (72) is responsive to a control code to establish a particular stepping sequence. In a longer sequence, the lowest priority requester is given the highest priority once and higher priority requesters are given the highest priority several times so that in a complete cycle of steps the requesters have a different relative priority. In shorter cycles, the lowest priority requester is still given highest priority once and the higher priority requesters are given highest priority a few times so that in the shorter cycles the lowest priority requester has a higher relative priority. The priority circuit also includes means (48-53) for matching a request for a resource with the availability of the resource so that a requester contends for priority only if the resource is in fact available.

    摘要翻译： 优先电路处理数据处理系统的三个组件的请求，以访问系统的几个资源，该系统的每个操作周期可以一次访问一个。 逻辑电路接收请求者（30-32）的请求，并优先地向一个请求者授予接入（64-66）。 逻辑电路具有用于建立特定优先级序列的装置（39,62,63），并且优先级电路包括用于通过不同优先顺序的周期对逻辑电路进行步进的装置（69,72,73）。 在这些步骤的重复周期中，每个请求者被给予最高优先级至少一次。 步进装置（72）响应于控制代码以建立特定的步进序列。 在较长的序列中，最低优先级请求者被给予最高优先级，一次优先级请求者被给予最高优先级，以便在完整的步骤周期中，请求者具有不同的相对优先级。 在较短的周期中，最低优先级请求者仍然被赋予最高优先级，并且较高优先权请求者被给予最高优先级几次，使得在较短的周期中，最低优先权请求者具有较高的相对优先级。 优先级电路还包括用于将资源的请求与资源的可用性进行匹配的装置（48-53），使得只有当资源实际上可用时，请求者才竞争优先级。

    Serial keyboard interface system
    37.
    发明公开
    Serial keyboard interface system 失效
    Serielles Schnittstellen-Tastatursystem。

    公开(公告)号：EP0114998A2

    公开(公告)日：1984-08-08

    申请号：EP83112634.7

    申请日：1983-12-15

    申请人： International Business Machines Corporation

    发明人： Tajima, Satoshi ,  Watanabe, Shinpei ,  Suzuki, Toshio ,  Yanagi, Tsutomu ,  Yonemochi, Kenshin

    IPC分类号： G06F11/00

    CPC分类号： G06F11/076 ,  G06F3/023 ,  H03M11/20

    摘要： A keyboard interface for a data processing system in which a keyboard (6) and a data processing unit (8) are connected through a single clock line (4) for transmitting a keyboard out clock signal and a single data line (2) for transmitting a serial bit frame having a serial scan code identifying a depressed key in synchronism with the clock signal is disclosed. The interface uses a transmission error detection and resend procedure to prevent transmission error due to noise pulse induced on the clock line (4) as by electrostatic discharge to give rise to extra data sampling. The unit returns a status signal acknowledging the receipt of a frame to the keyboard (6) through the data line (2) immediately after the number of sampled bits received by the unit reaches the predetermined number of bits of a frame. The keyboard checks whether the status signal has been returned after the completion of transmission of a frame and, if not, returns a negative response to the unit through the clock line, then resending the same scan code. The interface permits the use of a low cost, low noise- tolerance stretch cable without shield.

    摘要翻译： 一种用于数据处理系统的键盘接口，其中键盘（6）和数据处理单元（8）通过单个时钟线（4）连接，用于发送键盘输出时钟信号和用于发送的单个数据线（2） 公开了一种具有识别与时钟信号同步的按键的串行扫描码的串行比特帧。 该接口使用传输错误检测和重发程序，以防止由于静电放电引起的时钟线（4）上的噪声脉冲引起的传输错误，从而产生额外的数据采样。 在单元接收到的采样比特数达到帧的预定位数之后，该单元立即通过数据线（2）将确认接收到帧的状态信号返回到键盘（6）。 键盘在完成帧的传输后，检查状态信号是否已经返回，如果不是，则通过时钟线返回到本机的负响应，然后重新发送相同的扫描码。 该接口允许使用低成本，低噪音的拉伸电缆，而不需要屏蔽。