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公开(公告)号:EP3447556A3
公开(公告)日:2019-03-27
申请号:EP18194958.7
申请日:2017-02-17
发明人: HEMENWAY, Roe , STAGARESCU, Cristian , MEEROVICH, Daniel , GREEN, Malcolm, R. , PARZ, Wolfgang , MA, Jichi , GRZYBOWSKI, Richard Robert , BICKEL, Nathan
摘要: Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.
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32.
公开(公告)号:EP3241260A1
公开(公告)日:2017-11-08
申请号:EP15875928.2
申请日:2015-12-02
IPC分类号: H01S3/10
CPC分类号: H04Q11/0066 , H01S5/0428 , H04B10/502 , H04B10/504 , H04Q2011/0033 , H04Q2011/0035 , H04Q2011/0086
摘要: An optical signal module including a driver and an optical signal module. The driver includes a differential pair configured to receive and process an input signal to create a drive signal. A modulation current source provides a modulation current to the differential pair. One or more termination resistors connected to the differential pair for impedance matching. A first switch, responsive to a first control signal, maintains charge on a charge storage device. The optical signal module includes an optical signal generator arranged between a supply voltage node and a bias current node. The optical signal generator receives the drive signal and generates an optical signal representing the input signal. A second switch is between a supply voltage node the bias current node. The second switch, responsive to second control signal, selectively establishes a short between the supply voltage node the bias current node.
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公开(公告)号:EP3804247B1
公开(公告)日:2024-08-14
申请号:EP19811970.3
申请日:2019-05-30
IPC分类号: H04L25/02
CPC分类号: H04L25/0266 , H04L25/0278 , H04L25/0272
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公开(公告)号:EP4385151A1
公开(公告)日:2024-06-19
申请号:EP22761739.6
申请日:2022-08-02
发明人: DRAPER, Daniel , BROWNLEE, Merrick
IPC分类号: H04B10/079 , H04B10/50 , H04B10/54 , H04B10/58
CPC分类号: H04B10/0799 , H04B10/50572 , H04B10/54 , H04B10/58
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35.
公开(公告)号:EP4364188A2
公开(公告)日:2024-05-08
申请号:EP22747484.8
申请日:2022-06-28
发明人: LONG, Rathnait , STRUBLE, Wayne , CARLSON, Douglas
CPC分类号: H01L2224/1614520130101 , H01L2224/1622720130101 , H01L2224/1301420130101 , H01L2224/1301220130101 , H01L24/11 , H01L24/13 , H01L2224/1301320130101 , H01L23/3171 , H01L2224/1301720130101 , H01L2224/1301920130101 , H01L2224/1301520130101 , H01L2224/039120130101 , H01L24/742 , H01L2224/1131220130101 , H01L2224/1190120130101 , H01L24/14 , H01L2224/1405120130101 , H01L2224/1413520130101 , H03H3/04 , H03H2003/044220130101 , H03H9/0523 , H03H3/02 , H01L24/05 , H01L2224/040120130101 , H01L24/16 , H01L2224/113120130101 , B33Y10/00 , B33Y80/00 , B22F10/10 , H03H2003/02320130101 , H01L2224/0564720130101 , H01L2224/1315720130101 , H01L2224/1317620130101 , H01L2224/1312420130101 , H01L2224/13120130101 , H01L2224/0564420130101 , H01L2224/0568120130101 , H01L2224/0566420130101 , H01L2224/1311120130101 , H01L2224/1314420130101 , H01L2224/0563920130101 , H01L2224/1316620130101 , H01L2224/1318120130101 , H01L2224/1318420130101 , H01L2224/1313920130101 , H01L2224/0568420130101 , H01L2224/0562420130101 , H01L2224/1314720130101
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公开(公告)号:EP3577758B1
公开(公告)日:2024-04-03
申请号:EP17734137.7
申请日:2017-02-02
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公开(公告)号:EP3616320B1
公开(公告)日:2023-11-08
申请号:EP17728258.9
申请日:2017-04-24
发明人: CASSOU, Christian , BOUISSE, Gerard
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公开(公告)号:EP3443597B1
公开(公告)日:2021-07-07
申请号:EP17733109.7
申请日:2017-04-14
IPC分类号: H01L29/872 , H01L21/329 , H01L29/40 , H01L29/205 , H01L29/47
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公开(公告)号:EP2789060B1
公开(公告)日:2021-05-19
申请号:EP12855851.7
申请日:2012-12-03
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公开(公告)号:EP3742607A1
公开(公告)日:2020-11-25
申请号:EP20178902.1
申请日:2016-09-26
发明人: NAGY, Walter H. , PATTISON, Lyndon
摘要: Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.
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