公开(公告)号：EP1892753A3

公开(公告)日：2009-04-29

申请号：EP07016503.0

申请日：2007-08-22

Applicant: Kovio, Inc.

Inventor： Kamath, Arvind ,  Smith, Patrick ,  Cleeves, James Montague

IPC: H01L21/336 ,  H01L29/788 ,  H01L21/208 ,  H01L21/288 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

Abstract: A nonvolatile memory cell is disclosed, having first (2) and second (3) semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island (2) providing a control gate and the second semiconductor island (3) providing source and drain terminals; a gate dielectric layer (4) on at least part of the first semiconductor island (2); a tunneling dielectric layer (5) on at least part of the second semiconductor island (3); a floating gate (7) on at least part of the gate dielectric layer (4) and the tunneling dielectric layer (5); and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an "all-printed" process technology.

公开(公告)号：EP2040292A1

公开(公告)日：2009-03-25

申请号：EP07790682.4

申请日：2007-07-12

Applicant: Unisantis Electronics (Japan) Ltd. ,  Tohoku University

Inventor： MASUOKA, Fujio ,  NAKAMURA, Hiroki

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0416 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells.
The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor memory cells are arranged in a matrix, each nonvolatile semiconductor memory cell having an island semiconductor layer in which a drain diffusion layer formed in the upper part of the island semiconductor layer, a source diffusion layer formed in the lower part of the island semiconductor layer, a charge accumulation layer formed on a channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge accumulation layer are formed. Further, bit lines connected to the drain diffusion layer are laid out in a column direction, control gate lines are laid out in a row direction, and source lines connected to the source diffusion layer are laid out in the column direction.

Abstract translation: 为了提供一种NOR型非易失性半导体存储器，其可以通过使用FN隧道电流将电荷注入到电荷累积层中，而不损害存储器单元的封装密度的增加。 上述问题通过其中非易失性半导体存储单元排列成矩阵的非易失性半导体存储器来解决，每个非易失性半导体存储单元具有岛状半导体层，其中在岛状半导体层的上部中形成漏极扩散层， 在所述岛状半导体层的下部形成的源极扩散层，隔着栅极绝缘膜夹在所述漏极扩散层与所述源极扩散层之间的所述侧壁的沟道区域上的电荷蓄积层， 形成电荷累积层。 此外，连接到漏极扩散层的位线在列方向上布置，控制栅极线在行方向上布置，并且连接到源极扩散层的源极线在列方向上布置。

公开(公告)号：EP1939942A2

公开(公告)日：2008-07-02

申请号：EP07150240.5

申请日：2007-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song, Seung-hwan, c/o ,  Kim, Suk-pil, c/o ,  Park, Yoon-dong, c/o ,  Kim, Won-joo, c/o ,  Koo, June-mo, c/o ,  Cho, Kyoung-lae, c/o ,  Hyun, Jae-woong, c/o ,  Byun, Sung-jae, c/o

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract translation: 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对作为活性区域使用（或功能）的翅片。 半导体柱可以插入翅片的部分之间以连接翅片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

公开(公告)号：EP1932171A1

公开(公告)日：2008-06-18

申请号：EP06821149.9

申请日：2006-09-26

Applicant: NXP B.V.

Inventor： GOARIN, Pierre

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L29/786

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

Abstract: A non- volatile memory device on a substrate layer (2) comprises source and drain regions (3) and a channel region (4). The source and drain regions (3) and the channel region (4) are arranged in a semiconductor layer (20) on the substrate layer (2). The channel region (4) is fin-shaped and extends longitudinally (X) between the source region and the drain region (3). The channel region (4) comprises two fin portions (4a, 4b) and an intra-fin space (10), the fin portions (4a, 4b) extending in the longitudinal direction (X) and being spaced apart , and the intra- fin space (10) being located in between the fin portions (4a, 4b), and a charge storage area (11, 12; 15, 12) is located in the intra-fin space (10) between the fin portions (4a, 4b).

公开(公告)号：EP1908108A2

公开(公告)日：2008-04-09

申请号：EP06774620.6

申请日：2006-07-12

Applicant: Micron Technology, Inc.

Inventor： BHATTACHARYYA, Arup

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/8246 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/513 ,  H01L29/7881

Abstract: Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non- volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate- stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

公开(公告)号：EP1760792A1

公开(公告)日：2007-03-07

申请号：EP06119075.7

申请日：2006-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seol, Kwang Soo ,  Cho, Kyung Sang ,  Kim, Byung Ki ,  Lee, Eun Hye ,  Choi, Jae Young

IPC: H01L29/788 ,  H01L21/8247

CPC classification number: B82Y10/00 ,  H01L29/42332 ,  H01L29/7881

Abstract: Disclosed are a nanodot memory formed by applying a metal nanodot colloid solution, which is in a colloidal state, on a semiconductor substrate and thus uniformly arranging nanodot particles with a size of several nanometers on the semiconductor substrate in order to increase the integrity of the memory, and a fabrication method thereof. In the nanodot memory fabrication method, a first insulating film is formed on a surface of a substrate, and a metal nanodot colloid solution is applied on the first insulating film. Subsequently, a solvent inside the metal nanodot colloid solution is evaporated to form a nanodot particles layer, and a second insulating film is formed on the substrate, on the surface of which the nanodot particles are exposed. At this time, the nanodot particles are formed in a monolayer structure by adjusting concentration of metal nanodot particles contained within the metal nanodot colloid solution. By applying a metal nanodot colloid solution on a semiconductor substrate by means of a spin coating method to form monolayer nanodot particles with uniform arrangement, a nanodot memory having a nanodot structure can be easily fabricated.

Abstract translation: 公开了通过在半导体衬底上施加胶体状态的金属纳米棒胶体溶液并因此在半导体衬底上均匀排列尺寸为几纳米的纳米点颗粒而形成的纳米点存储器，以增加存储器的完整性 ，及其制造方法。 在纳米点存储器制造方法中，在基板的表面上形成第一绝缘膜，并且在第一绝缘膜上施加金属纳米棒胶体溶液。 随后，蒸发金属纳米棒胶体溶液内的溶剂，形成纳米点粒子层，在基板上形成第二绝缘膜，其表面上露出纳米点粒子。 此时，通过调整金属纳米点胶体溶液中所含的金属纳米点粒子的浓度，使纳米点粒子成为单层结构。 通过利用旋涂法在半导体衬底上施加金属纳米棒胶体溶液以形成具有均匀排列的单层纳米点颗粒，可以容易地制造具有纳米点结构的纳米点存储器。

公开(公告)号：EP1671365A2

公开(公告)日：2006-06-21

申请号：EP04794293.3

申请日：2004-10-06

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： BAWENDI, Moungi, G. ,  BULOVIC, Vladimir ,  COE, Seth, A.

IPC: H01L21/336 ,  H01L29/80

CPC classification number: G11C13/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C16/0466 ,  G11C2213/12 ,  G11C2213/18 ,  G11C2213/53 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/127 ,  H01L29/2203 ,  H01L29/42332 ,  H01L29/7881

Abstract: A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

Abstract translation: 存储器件可以包括具有可选横向导电率的有源层。 该层可以包括多个纳米颗粒。

公开(公告)号：EP1364393A4

公开(公告)日：2006-06-07

申请号：EP02720896

申请日：2002-02-04

Applicant: MICRON TECHNOLOGY INC

Inventor： FORBES LEONARD ,  AHN KEI Y

IPC: H01L21/28 ,  H01L21/764 ,  G11C16/04 ,  G11C16/28 ,  H01L21/20 ,  H01L21/225 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66666 ,  G11C16/0416 ,  G11C16/28 ,  H01L21/28273 ,  H01L27/11556 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Structures and method for Flash memory with ultra thin vertical body transistors (200) are provided. The Flash memory includes an array of memory cells including floating gate transistors (200). Each floating gate transistor (200) includes a pillar (201) extending outwardly from a semiconductor substrate (202). The pillar (201) includes a single crystalline first contact layer (204) and a second contact layer (206) vertically separated by an oxide layer (208). A single crystalline vertical transistor (210) is formed along side of the pillar. The single crystalline vertical transistor (210) includes an ultra thin single crystalline vertical body region (212) which separates an ultra thin single crystalline vertical first source/drain region (214) and an ultra thin single crystalline vertical second source/drain region (216). A floating gate (212) opposes the ultra thin single crystalline vertical body region (212), and a control gate (218) separated from the floating gate (212) by an insulator layer (220).

公开(公告)号：EP1556866A1

公开(公告)日：2005-07-27

申请号：EP03770742.9

申请日：2003-10-09

Applicant: SanDisk Corporation

Inventor： HARARI, Eliyahou

IPC: G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

公开(公告)号：EP1535336A2

公开(公告)日：2005-06-01

申请号：EP03793747.1

申请日：2003-08-21

Applicant: Infineon Technologies AG

Inventor： HOFMANN, Franz ,  LANDGRAF, Erhard ,  LUYKEN, Richard, Johannes ,  RÖSNER, Wolfgang ,  SPECHT, Michael

IPC: H01L27/115

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

Abstract: The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1).