公开(公告)号：EP2847794B1

公开(公告)日：2017-12-27

申请号：EP13787091.1

申请日：2013-05-07

申请人： Micron Technology, Inc.

发明人： SANDHU, Gurtej S.

IPC分类号： H01L45/00

CPC分类号： H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/52 ,  G11C2213/53 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state.

公开(公告)号：EP2577668A2

公开(公告)日：2013-04-10

申请号：EP11792836.6

申请日：2011-05-06

申请人： Micron Technology, Inc.

发明人： LIU, Zengtao

IPC分类号： G11C7/18 ,  G11C8/14 ,  G11C5/02 ,  H01L21/8239

CPC分类号： G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

公开(公告)号：EP2577668A4

公开(公告)日：2014-01-22

申请号：EP11792836

申请日：2011-05-06

申请人： MICRON TECHNOLOGY INC

发明人： LIU ZENGTAO

IPC分类号： G11C7/18 ,  G11C5/02 ,  G11C7/10 ,  G11C8/14 ,  H01L21/8239

CPC分类号： G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

公开(公告)号：EP1671365A4

公开(公告)日：2008-08-13

申请号：EP04794293

申请日：2004-10-06

申请人： MASSACHUSETTS INST TECHNOLOGY

发明人： BAWENDI MOUNGI G ,  BULOVIC VLADIMIR ,  COE SETH A

IPC分类号： H01L21/336 ,  G11C13/02 ,  G11C16/04 ,  H01L20060101 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/80 ,  H01L31/0336

CPC分类号： G11C13/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C16/0466 ,  G11C2213/12 ,  G11C2213/18 ,  G11C2213/53 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/127 ,  H01L29/2203 ,  H01L29/42332 ,  H01L29/7881

摘要： A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

公开(公告)号：EP1723676A2

公开(公告)日：2006-11-22

申请号：EP05758741.2

申请日：2005-03-09

申请人： Nanosys, Inc.

发明人： DUAN, Xiangfeng ,  CHOW, Calvin, Y., H. ,  HEALD, David, L. ,  NIU, Chunming ,  PARCE, J., Wallace ,  STUMBO, David, P.

IPC分类号： H01L29/06

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

公开(公告)号：EP1159761A1

公开(公告)日：2001-12-05

申请号：EP00913530.2

申请日：2000-02-18

申请人： Clawson, Joseph E., Jr.

发明人： Clawson, Joseph E., Jr.

IPC分类号： H01L29/06 ,  B01D17/06 ,  G01N23/00

CPC分类号： H01L27/283 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C13/025 ,  G11C2213/18 ,  G11C2213/81 ,  H01L51/0048 ,  H01L51/0595

摘要： A nanodevice is disclosed wherein the gating member (150, 153'-157) can be either transverse to the conducting nanotube (150), or substantially surround the conducting nanotube (153'-157). A pseudo P-channel nanoswitch construction (150-151-152-153) as well as pseudo-CMOS nanoinverters (170-171-173-174-177-179) are disclosed and a nanomultivibrator (170-171-174-179-170'-171'-174'-179') and nanomultivibrator frequency dividing chain (174-190-190'-192-193) are disclosed operating in the sub-picosecond region. A pseudo P-channel enhancement mode power device (259, 259') is disclosed and is preferably used with an RC time constant compensation scheme (247i, 241i) to provide substantially simultaneous switching over the entire power nanoswitch (259, 259'). Nanotube separationand alignment apparati (300, 300') are disclosed, as well as improved atomic microscope probes (281-282-283-284-285-286-287, 291-292-293-294-295-297-298) and heads (310) to make and use the invention.

公开(公告)号：EP1671365B1

公开(公告)日：2018-12-05

申请号：EP04794293.3

申请日：2004-10-06

申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY

发明人： BAWENDI, Moungi, G. ,  BULOVIC, Vladimir ,  SETH A. Coe-Sullivan

IPC分类号： H01L21/336 ,  H01L29/80 ,  G11C13/02 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/12 ,  H01L29/22

CPC分类号： G11C13/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C16/0466 ,  G11C2213/12 ,  G11C2213/18 ,  G11C2213/53 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/127 ,  H01L29/2203 ,  H01L29/42332 ,  H01L29/7881

摘要： A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

公开(公告)号：EP2299482A3

公开(公告)日：2014-12-17

申请号：EP10188252.0

申请日：2004-10-06

申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY

发明人： Bawendi, Moungi G. ,  Bulovic, Vladimir ,  Coe-Sullivan, Seth A.

IPC分类号： H01L29/423

CPC分类号： G11C13/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C16/0466 ,  G11C2213/12 ,  G11C2213/18 ,  G11C2213/53 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/127 ,  H01L29/2203 ,  H01L29/42332 ,  H01L29/7881

摘要： A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

公开(公告)号：EP2299482A2

公开(公告)日：2011-03-23

申请号：EP10188252.0

申请日：2004-10-06

申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY

发明人： Bawendi, Moungi G. ,  Bulovic, Vladimir ,  Coe-Sullivan, Seth A.

IPC分类号： H01L21/336 ,  H01L29/80

CPC分类号： G11C13/02 ,  B82Y10/00 ,  B82Y30/00 ,  G11C16/0466 ,  G11C2213/12 ,  G11C2213/18 ,  G11C2213/53 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/127 ,  H01L29/2203 ,  H01L29/42332 ,  H01L29/7881

摘要： A memory device can include an active layer that has a selectable lateral conductivity. The layer can include a plurality of nanoparticles.

摘要翻译： 存储器件可以包括具有可选择的侧向电导率的有源层。 该层可以包括多个纳米颗粒。

公开(公告)号：EP1159761A4

公开(公告)日：2006-04-19

申请号：EP00913530

申请日：2000-02-18

申请人： CLAWSON JOSEPH E JR

发明人： CLAWSON JOSEPH E JR

IPC分类号： H01L51/30 ,  B82B3/00 ,  C01B31/02 ,  G01N23/00 ,  G11C13/02 ,  H01L27/28 ,  H01L29/06 ,  H01L29/15 ,  H01L29/16

CPC分类号： H01L27/283 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C13/025 ,  G11C2213/18 ,  G11C2213/81 ,  H01L51/0048 ,  H01L51/0595

摘要： A nanodevice is disclosed wherein the gating member (150, 153'-157) can be either transverse to the conducting nanotube (150), or substantially surround the conducting nanotube (153'-157). A pseudo P-channel nanoswitch construction (150-151-152-153) as well as pseudo-CMOS nanoinverters (170-171-173-174-177-179) are disclosed and a nanomultivibrator (170-171-174-179-170'-171'-174'-179') and nanomultivibrator frequency dividing chain (174-190-190'-192-193) are disclosed operating in the sub-picosecond region. A pseudo P-channel enhancement mode power device (259, 259') is disclosed and is preferably used with an RC time constant compensation scheme (247i, 241i) to provide substantially simultaneous switching over the entire power nanoswitch (259, 259'). Nanotube separationand alignment apparati (300, 300') are disclosed, as well as improved atomic microscope probes (281-282-283-284-285-286-287, 291-292-293-294-295-297-298) and heads (310) to make and use the invention.

摘要翻译： 公开了一种纳米器件，其中所述选通构件（150,153'-157）可以横向于所述导电纳米管（150），或者基本上围绕所述导电纳米管（153'-157）。 公开了一种伪P沟道纳米开关结构（150-151-152-153）以及伪CMOS纳米变换器（170-171-173-174-177-179），并且纳米多谐振荡器（170-171-174-179- 170'-171'-174'-179'）和纳米多谐振子分频链（174-190-190'-192-193）在亚皮秒区域中运行。 公开了一种伪P信道增强型功率器件（259,259'），并且优选地使用RC时间常数补偿方案（247i，241i）来提供对整个功率纳秒开关（259,259'）的基本上同时的切换。 公开了纳米管分离和取向装置（300,300'），以及改进的原子显微镜探针（281-282-283-284-285-286-287,291-292-293-294-295-297-298）和 头（310）制造和使用本发明。