公开(公告)号：EP2482461A3

公开(公告)日：2013-03-27

申请号：EP12152538.0

申请日：2012-01-25

申请人： Cambridge Silicon Radio Limited

发明人： Zare-Hoseini, Hashem ,  Williams, Peter

IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M3/04

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464

摘要： The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.

公开(公告)号：EP2482461A2

公开(公告)日：2012-08-01

申请号：EP12152538.0

申请日：2012-01-25

申请人： Cambridge Silicon Radio Limited

发明人： Zare-Hoseini, Hashem ,  Williams, Peter

IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M3/04

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464

摘要： The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.

摘要翻译： 本发明涉及一种多位数模转换器（DAC）以及采用这种DAC的Δ-Σ模数转换器。 DAC具有多位输入，用于处理在输入端接收的输入信号的多个元件和用于根据输入信号选择一个或多个DAC元件来处理信号的选择器。 DAC具有用于控制选择器的控制装置，使得如果DAC的输入在预定时间段内低于预定电平，则选择器仅可操作以仅选择DAC单元中的一个来处理输入信号。 还公开了采用这种DAC的Δ-Σ模数转换器（ADC）。

公开(公告)号：EP2269311A2

公开(公告)日：2011-01-05

申请号：EP09762966.1

申请日：2009-03-08

申请人： QUALCOMM Incorporated

发明人： SEO, Dongwon ,  McALLISTER, Gene H. ,  DABAG, Hayg-Taniel

IPC分类号： H03M1/06

CPC分类号： H03M1/004 ,  H03M1/066 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M3/502

摘要： According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

公开(公告)号：EP2237424A1

公开(公告)日：2010-10-06

申请号：EP09368009.8

申请日：2009-03-30

申请人： Dialog Semiconductor GmbH

发明人： Myles Andrew ,  Terry, Andrew

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/80

CPC分类号： H03M1/08 ,  H03M1/0665 ,  H03M1/806 ,  H03M3/502

摘要： Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

摘要翻译： 使用相同的实现三电平多位delta-sigma DAC的系统和方法具有降低的功耗和电压跌落havebeen实现。 一种新的基于旋转的一阶噪声整形动态元件匹配（DEM）技术用于与三电平的单位元件使用已经游离缺失盘。 降低基准加载已经实现当三电平DEM方案被应用于特别是开关电容器实现。 进一步更差分开关电容器DAC实施，这使得能够使用DEM技术的光盘是游离缺失。 本发明允许实现一个N位DAC当使用三电平单元元件构成需要减小电路的复杂性。

公开(公告)号：EP1033816B1

公开(公告)日：2004-12-29

申请号：EP99104180.7

申请日：1999-03-02

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Tani, Yasunori ,  Miyada, Yoshinori ,  Hyobu, Kazuyuki

IPC分类号： H03M1/06

CPC分类号： H03M1/0665 ,  H03M1/66

公开(公告)号：EP0401245B1

公开(公告)日：1995-06-07

申请号：EP89902275.0

申请日：1989-02-10

申请人： DATA CONVERSION SYSTEMS LIMITED

发明人： STOREY, Michael, John

IPC分类号： H03M1/74 ,  H03M1/06

CPC分类号： H03M1/0665 ,  H03M1/747

摘要： An n bit DAC of the kind having at least 2n-1 sources, typically current sources, especially for use in oversampling ADCs to enable a resolution accuracy in excess of 18 bits, wherein at least 2n-1 sources are switchable by at least 2n-1 switches responsively to inputs on at least 2n-1 digital input lines, and a source selection circuit, typically an at least 2n-1 to 2n-1 multiplexer, is connected between the digital input lines and the switches and is adapted to select the sources in a dynamic manner, based on a predetermined algorithm which converts DAC errors into noise and puts the noise energy into unwanted parts of the spectrum.

公开(公告)号：EP2454816B1

公开(公告)日：2018-11-28

申请号：EP10735390.6

申请日：2010-07-15

申请人： Microchip Technology Incorporated

发明人： DEVAL, Philippe ,  QUIQUEMPOIX, Vincent

IPC分类号： H03M3/00 ,  H03M1/06

CPC分类号： H03M1/0663 ,  H03M1/0665 ,  H03M3/422 ,  H03M3/456 ,  H03M3/464

摘要： A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.

公开(公告)号：EP3142255A1

公开(公告)日：2017-03-15

申请号：EP16154920.9

申请日：2016-02-09

申请人： Analog Devices Global

发明人： CHEN, Dong

IPC分类号： H03M1/06 ,  H03M1/66

CPC分类号： H03M1/0665 ,  H03M1/66

摘要： Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit of an ordered sequence of DAC units that are switched on to convert a particular digital value to an analog value. The mechanism benefits from recognition that selecting the first DAC based on a value of a bandlimited dither signal, where the band of the dither signal is selected to be sufficiently removed from the band of the signal of interest, allows shifting effects of DAC units mismatch away from the signal of interest in a manner that is easy to implement and control. Because dither signal is not added to the signal of interest, but is only used to control which DAC units are turned on, drawbacks of a traditional dithering method can be avoided while benefiting from the use of dither.

摘要翻译： 本公开描述了一种用于寻址DAC中的组件不匹配的改进机制。 该机制基于仔细选择接通的DAC单元的有序序列的第一DAC单元以将特定数字值转换为模拟值。 该机制受益于基于频带抖动信号的值选择第一DAC，其中抖动信号的频带被选择为从感兴趣的信号的频带中充分移除，允许DAC单元的偏移效应不匹配 从感兴趣的信号以易于实施和控制的方式。 由于抖动信号未被添加到感兴趣的信号，而是仅用于控制哪些DAC单元被接通，所以可以避免使用传统的抖动方法的缺点，同时受益于抖动的使用。

公开(公告)号：EP2974032A1

公开(公告)日：2016-01-20

申请号：EP14720287.3

申请日：2014-03-10

申请人： Microchip Technology Incorporated

发明人： QUIQUEMPOIX, Vincent

IPC分类号： H03M1/06 ,  H03M3/04

CPC分类号： H03M1/802 ,  H03M1/0665 ,  H03M3/30 ,  H03M3/424 ,  H03M3/464

摘要： A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+l output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.

摘要翻译： 用于Σ-Δ调制器中的电荷传输类型的数模转换器（DAC）包括可操作用于生成4n + 1输出电平的电容器开关单元，该电容器开关单元包括：多个第二开关单元，用于将 具有正参考信号或负参考信号的多个参考电容器对; 其中所述多个参考电容器对的第二端子分别并联耦合; 其中为了偶数传输，提供单个开关组合以实现线性，并且其中对于奇数传输，提供平均不同开关组合以实现线性; 其中偶数传输是当DAC的输入是偶数时并且奇数传输是当DAC的输入是奇数时。

公开(公告)号：EP2872997A2

公开(公告)日：2015-05-20

申请号：EP13816182.3

申请日：2013-06-12

申请人： Wispry, Inc.

发明人： MORRIS, Arthur, S., III

IPC分类号： G06F12/00

CPC分类号： H03H19/004 ,  H03J2200/10 ,  H03M1/0651 ,  H03M1/0665 ,  H03M1/0863 ,  H03M1/66

摘要： The present subject matter relates to methods, devices, and systems for switched capacitor array control. For an array of two-state elements that can be independently positioned in either an active state or an inactive state, the methods, devices, and systems can determine a linear number
D of elements in the active state needed to achieve a total combined activity corresponding to a desired behavior, compare a number
A of elements in an active state to the linear number
D of elements needed to achieve the desired behavior, activate a first number
n of inactive elements, and deactivate a second number
m of active elements, wherein the difference between the first number
n and the second number
m is equal to the difference between the linear number D of elements needed to achieve the desired behavior and the present number
A of elements in an active state.