公开(公告)号：EP2591555B1

公开(公告)日：2018-03-07

申请号：EP11700774.0

申请日：2011-01-11

申请人： Microchip Technology Incorporated

发明人： QUIQUEMPOIX, Vincent ,  JOHNER, Yann ,  BELLINI, Gabriele

IPC分类号： H03M3/00 ,  H03M1/06

CPC分类号： H03M1/0663 ,  H03M1/0665 ,  H03M3/422 ,  H03M3/456 ,  H03M3/464

摘要： A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.

公开(公告)号：EP2974029A1

公开(公告)日：2016-01-20

申请号：EP14712148.7

申请日：2014-03-06

申请人： Microchip Technology Incorporated

发明人： QUIQUEMPOIX, Vincent

IPC分类号： H03M1/06 ,  H03M3/04

CPC分类号： H03M1/0665 ,  H03M3/424 ,  H03M3/464

摘要： A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.

公开(公告)号：EP1142122B1

公开(公告)日：2006-09-27

申请号：EP00971357.9

申请日：2000-10-09

申请人： Koninklijke Philips Electronics N.V.

发明人： WESTRA, Jan, R. ,  ANNEMA, Anne, J.

IPC分类号： H03M1/06 ,  H03M1/74

CPC分类号： H03M1/0665 ,  H03M1/1205 ,  H03M1/747

摘要： A digital to analog converter for a multibit digital input signal has a set of conversion elements for the positive signal excursions and a set of conversion elements for the negative signal excursions. In each set the conversion elements are selected according to a dynamic element matching algorithm. To improve the mismatch-noise shaping of these algorithms, excess conversion elements may be additionally selected.

公开(公告)号：EP1391039A4

公开(公告)日：2005-12-07

申请号：EP02726798

申请日：2002-04-25

申请人： CIRRUS LOGIC INC

发明人： TUCKER JOHN CHRISTOPHER ,  CHOKHAWALA AMIYA ANAND ,  YANG YU QING ,  MELANSON JOHN LAURENCE

IPC分类号： H03M3/04 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/74 ,  H03M3/00

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464

摘要： A method and system of operating dynamic element matching ("DEM") system with two or more power supplies are disclosed. A connection system (12) of the DEM system is driven with one power supply operating at one voltage. Connection system couples to components that are to be matched and equalized in usage by ordering outputs to components and activating the components according to ordered outputs. A connection calculator (16) of the DEM system is driven with another power supply operating at another voltage different from the one voltage. Connection calculator is coupled to the connection system, and connection calculator calculates an order of usage of components. A level shifter system (14) level shifts voltage levels of signals from connection system to connection calculator, and another level shifter system (18) level shifts voltage levels of signals from connection calculator to connection system.

公开(公告)号：EP1359671A1

公开(公告)日：2003-11-05

申请号：EP03290985.5

申请日：2003-04-22

申请人： Thomson Licensing S.A.

发明人： Heizmann, Friedrich ,  Erbar, Maximilian

IPC分类号： H03M1/74 ,  H03M1/06

CPC分类号： H03M1/0665 ,  H03M1/747 ,  H03M3/502 ,  H03M7/165

摘要： The invention relates to a method for converting a digital signal an analogue signal and to a digital to analogue converter comprising means for converting a digital signal to a thermometer coded signal, means for randomising (5) the thermometer coded signal (4), means for controlling (6) the means for randomising based on the digital signal and means for converting (9) the randomised signal to analogue.

摘要翻译： 本发明涉及一种将模拟信号的数字信号转换成数模转换器的方法，包括用于将数字信号转换为温度计编码信号的装置，用于随机化（5）温度计编码信号（4）的装置， 控制（6）基于数字信号的随机化装置和用于将（9）随机信号转换为模拟的装置。

公开(公告)号：EP1331741A2

公开(公告)日：2003-07-30

申请号：EP03001663.8

申请日：2003-01-24

申请人： Broadcom Corporation

发明人： Kwan, Tom W.

IPC分类号： H03M1/06

CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/502

摘要： A data shuffler apparatus shuffles input bits to perform dynamic element matching, The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.

摘要翻译： 一种数据混洗设备，打乱输入比特来执行动态元件匹配，所述混洗器设备包括N个输入洗牌，每一个都具有输入洗牌N个输入端及N个输出端，每个输入洗牌机接收respectivement输入比特中的一个的每个输入端。 所以该装置包括N个输出洗牌，每一个都具有输出混洗N个输入端及N个输出端，所述输入和输出洗牌互连搜索没有每个每个输入洗牌机的N个输出端被连接到一个不同的respectivement输入端子 的N个输出洗牌。

公开(公告)号：EP1282235A2

公开(公告)日：2003-02-05

申请号：EP02012035.8

申请日：2002-05-31

申请人： ROBERT BOSCH GMBH

发明人： Lehr, Carsten ,  Nyenhuis, Detlev

IPC分类号： H03M1/06

CPC分类号： H03M1/0687 ,  H03M1/0665 ,  H03M1/747 ,  H03M3/502

摘要： Vorgeschlagen werden eine Anordnung und ein Verfahren zur Umsetzung einer diskreten Wertefolge in ein analoges Signal mit einer Mehrzahl im wesentlichen gleicher schaltbarer Quellen, die derart miteinander verbunden sind, dass sich ihre Ausgangssignale zu dem analogen Signal überlagern, mit einer Zuordnungsschaltung zur Zuordnung von Schaltzuständen der Quellen zu Werten der diskreten Wertefolge in Abhängigkeit sowohl der Werte der diskreten Wertefolge als auch vorangegangener Schaltzustände der schaltbaren Quellen, die oder das sich erfindungsgemäß dadurch auszeichnet, dass mindestens eine Mehrzahl der, insbesondere alle, Quellen mindestens drei voneinander verschiedene Schaltzustände aufweisen.
Gegenüber bekannten DWA-Systemen hat die Erfindung den Vorteil, dass ein bestimmter Wert K durch verschiedene Anzahl eingeschalteter Quellen darstellbar ist, so dass durch Streuungen in den Ausgangssignalen der Quellen untereinander verursachte Verzerrungen bzw. Fehler im analogen Ausgangssignal weniger stark hervortreten.

摘要翻译： 该装置具有连接在一起的大量基本上相同的源（21-24），因此它们的输出信号叠加到模拟信号（25）和电路（12），用于将源切换状态与离散值序列的值相关联，取决于值 的离散序列和可切换源的先前切换状态。 源的至少一些，优选地全部具有三个相互独立的切换状态。 AN还包括以下的独立权利要求：将离散值序列转换为模拟信号的方法。

公开(公告)号：EP1273102A1

公开(公告)日：2003-01-08

申请号：EP01927828.2

申请日：2001-03-28

申请人： Koninklijke Philips Electronics N.V.

发明人： NUIJTEN, Petrus, A., C., M.

IPC分类号： H03M1/06

CPC分类号： H03M1/0651 ,  H03M1/0665 ,  H03M1/74

摘要： A digital to analog converter for a multi bit digital input signal with a plurality of substantially equal conversion elements which are selected in accordance with a dynamic element matching algorithm. The dynamic element matching algorithm is adapted to the position of the conversion elements on the semiconductor chip to improve the shaping of the noise caused by the systematic, i.e. position dependent, errors of the conversion elements.

公开(公告)号：EP3288186A1

公开(公告)日：2018-02-28

申请号：EP17151790.7

申请日：2017-01-17

申请人： MediaTek Inc.

发明人： SHU, Yun-Shiang

IPC分类号： H03M1/06 ,  H03M1/66 ,  H03M1/42 ,  H03M1/46

CPC分类号： H03M1/0626 ,  H03M1/0612 ,  H03M1/0665 ,  H03M1/42 ,  H03M1/468 ,  H03M1/66

摘要： The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit couple to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.

摘要翻译： 本发明提供了一种用于在具有失配误差整形的模拟域和数字域之间进行转换的系统，包括DAC，耦合到DAC的第一注入电路以及耦合到DAC的第二注入电路。 DAC响应于第一数字值产生第一模拟值，并且响应于第二数字值产生第二模拟值。 当DAC产生第二模拟值时，第一注入电路使得能够将模拟注入值注入到第二模拟值，其中，模拟注入值从由第一数字值的位子集形成的数字注入值转换。 第二注入电路将数字注入值注入第二数字值，或将数字注入值与根据第二模拟值获得的相关值组合。

公开(公告)号：EP3206159A4

公开(公告)日：2018-01-10

申请号：EP16856557

申请日：2016-01-21

申请人： SHENZHEN GOODIX TECH CO LTD

发明人： TAN BO

IPC分类号： G06K9/00 ,  H03M1/06

CPC分类号： G06K9/00087 ,  G06F3/044 ,  G06K9/0002 ,  H03M1/0665

摘要： The present invention provides an output conversion circuit and a fingerprint identification system. The output conversion circuit includes: a comparator, a counter, and a reference signal generator, where the counter includes: a first input end, configured to receive a first output signal; a second input end; and an output end, configured to generate a comparison output signal; the counter is connected to the output end of the comparator, and configured to generate a second output signal; and the reference signal generator is connected to the second input end, and configured to generate a reference signal, where the reference signal generator includes a random digit generator configured to generate a random digit, and the reference signal is associated with the random digit; where the comparator generates the comparison output signal according to the first output signal and the reference signal. The output conversion circuit provided in the present invention has an advantage of improving statistical linearity of an output signal.