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公开(公告)号：EP4380059A1
公开(公告)日：2024-06-05
申请号：EP23212145.9
申请日：2023-11-24
发明人： SAARI, Daniel Henrik
IPC分类号： H03M1/10
CPC分类号： H03M1/1028 , H03M1/109
摘要： An analog-to-digital converter (ADC) system for providing a calibrated voltage measurement without an external reference voltage may include an ADC circuit, including an analog ADC input and a digital ADC output. The ADC system may also include circuitry to generate a first internal reference voltage and a second internal reference voltage. The ADC system may also include circuitry configured to provide a selected output from a number of inputs, wherein the inputs include inputs to receive (1) the first internal reference voltage, (2) the second internal reference voltage, and (3) a user-provided analog signal of interest, wherein the selected output can be connected to the analog ADC input, an external voltage measurement device, or both.
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32.发明公开Method and circuit for bandwidth mismatch estimation in an a/d converter 有权的方法和电路用于在A / D转换器的带宽失配估计
公开(公告)号：EP2953265A1
公开(公告)日：2015-12-09
申请号：EP14171580.5
申请日：2014-06-06
申请人： IMEC VZW
CPC分类号： H03M1/0604 , H03M1/00 , H03M1/002 , H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/1215 , H03M1/14 , H03M1/468 , H03M2201/4233
摘要： The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising
- precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,
- setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals,
- applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,
- quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,
- comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch.-
公开(公告)号：EP2235833A2
公开(公告)日：2010-10-06
申请号：EP08702640.7
申请日：2008-01-14
申请人： DSP Group Ltd.
发明人： ITKIN, Yuval
CPC分类号： H03M1/109 , H03M1/1028 , H03M1/12 , H03M1/66
摘要： An apparatus and method for testing a unit comprising of digital-to-analog converter (208) and an analog-to-digital converter (212), by determining offset and gain- difference (220) between the two converters (2108, 212), and then testing the pair using a wide range of values During the testing (Fig 6), the gain-control is injected into the unit in order to set the unit size of one of the converters, and the offset is subtracted from the output signal of the unit, so that the transfer functions of the converters are matched The gain-control is optionally determined using the successive approximation algorithm.
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公开(公告)号：EP1568138B1
公开(公告)日：2007-03-07
申请号：EP03785625.9
申请日：2003-10-16
发明人： BOGNER, Peter
IPC分类号： H03M1/10
摘要： Disclosed is a device for calibrating A/D converters with any bit weight. The invention more specifically relates to an A/D converter for converting an analog input signal (ain) into a digital output value by means of at least one converter stage comprising a sample & hold circuit (3) for sampling the analog input signal (Ain), a comparator unit (5) which compares the analog input signal with a reference value (REF) so as to generate a digital output value of the converter stage, a digital/analog converter (13) for converting the digital output value into an analog signal, a subtractor (11) for subtracting the analog signal that is output by the digital/analog converter (13) from the sampled input signal, a signal amplifier (17) for amplifying the output signal output by the subtractor (11) by a specific signal-amplifying factor (V) for the following converter stage, and a weighting unit (9) for multiplying the digital output value by a multiplier in order to add the multiplied digital output value to other weighted output values of converter stages so as to obtain the digital output value of the analog/digital converter (1); (b) a random signal generator (19) for generating a random signal that is fed to the converter stage; (c) at least one calibrating unit (21) comprising: (c1) a calibration amplifier with an adjustable calibration amplification factor for amplifying the random signal; (c2) an evaluation unit which correlates the random signal that is fed into the signal path and amplified by the converter stage with the random signal amplified by the calibration amplifier of the calibration unit (21) in order to generate a signal for adjusting the calibration amplification factor such that the output signal of the evaluation unit is minimal, the calculated calibration amplification factor thus corresponding with the amplification (V) caused by the digital/analog converter (13) and the signal amplifier (17) of the converter stage; (d) the random signal is applied by the random generator (19) to a calibration capacitor (31) located within the digital/analog converter (13) of the converter stage via a switch that is controlled by the calibration unit (21) so as to be fed into the signal path; (e) the random signal can be connected to additional DAC capacitors (25) located within the digital/analog converter (13) in order to calculate the respective signal amplifications of the DAC stages of the digital/analog converter (13) while the calibration unit (21) calculates the signal amplification differences DeltaVIJ between the DAC stages from the determined signal amplifications (VI) of the DAC stages of the digital/analog converter (13) so as to calculate a switching error (DAC error) of the digital/analog converter (13).
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公开(公告)号：EP1568138A2
公开(公告)日：2005-08-31
申请号：EP03785625.9
申请日：2003-10-16
发明人： BOGNER, Peter
IPC分类号： H03M1/06
摘要： The invention relates to an A/D converter comprising at least one converter stage for converting an analog input signal (a-in) into a digital output value. Each converter stage is provided with a sample & hold circuit (3) for sampling the analog input signal (a-in), a comparator unit (5) which compares the analog input signal with a reference value (REF) so as to generate a digital output value of the converter stage, a digital/analog converter (13) for converting the digital output value into an analog signal, and a subtractor (11) for subtracting the analog signal that is output by the digital/analog converter (13) from the sampled input signal that is amplified and weighted before being added to the resulting digital value. The A/D converter is calibrated, a pseudo-random signal (PSR) being fed to a calibration unit based on a variable calibration amplifier which controls a switch (32) that supplies the pseudo-random signal to a calibration capacitor (31) and other DAC capacitors (25) in order to calculate the signal amplifications of the DAC stages. The calibration unit (21) calculates the signal amplification differences between the DAC stages from the determined signal amplifications of the DAC stages so as to calculate a switching error of the digital/analog converter (13).
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36.发明授权PROCEDE ET DISPOSITIF DE TEST INTEGRE POUR UN CONVERTISSEUR ANALOGIQUE-NUMERIQUE 有权综合测试安排模拟数字转换器及相应方法
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公开(公告)号：EP1145442A3
公开(公告)日：2002-03-06
申请号：EP00959482.1
申请日：2000-08-28
发明人： MICHEL, Jean-Yves
IPC分类号： H03M1/10
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38.发明公开Dispositif et procédé de contrôle de condensateurs intégrés 有权Vorrichtung und Verfahren zumÜberprüfenvon integrierten Kondensatoren
公开(公告)号：EP1162748A1
公开(公告)日：2001-12-12
申请号：EP01401421.1
申请日：2001-05-31
IPC分类号： H03M1/10
摘要： Le dispositif comprend une structure capacitive SCA possédant un noeud d'entrée ND 0 et n noeuds de sortie ND i , r condensateurs intégrés C connectés en série entre deux noeuds voisins, un condensateur intégré C connecté entre le noeud d'entrée ND 0 et la masse, un condensateur intégré C connecté entre le n ème noeud de sortie ND 1 et la masse, r branches capacitives BR i connectées en parallèle entre la masse et chaque noeud de la structure capacitive incluant le premier noeud de sortie ND 1 et le n-1 ème noeud de sortie ND n-1 , chaque branche BR i comportant r+1 condensateurs intégrés C connectés en série, tous les condensateurs C de la structure capacitive étant théoriquement identiques.
Des moyens de charge MCH chargent chaque noeud de la structure capacitive. Des moyens de mesure S i , Amp mesurent la charge en chacun des noeuds de la structure, et des moyens de comparaison comparent chaque valeur nodale de charge mesurée avec une valeur nodale de charge théorique compte tenu d'une tolérance nodale prédéterminée.摘要翻译： 控制装置（DCA）包括具有输入节点（ND0）和n个输出节点（ND1，...，NDn）的电容结构（SCA），其中n大于或等于2，则r个积分电容器（C） 在相邻节点之间串联连接，其中r大于或等于1，例如。 r = 1，连接在输入节点和地之间以及输出与地面的第n个节点之间的集成电容器（C），r电容分支并联连接在地和每个节点之间，包括第一节点 输出和输出的第（n-1）个节点，其中每个分支BRi（i = 1，...，n-1）包括r + 1，例如。 串联连接的集成电容器（C）和全部电容器（C）在理论上是相同的。 该装置还包括包括参考电压源（STR）和受控开关（Sv）的充电装置（MCH），测量装置包括电流表（Amp）和受控开关（Si），以及比较装置 考虑到预定的公差，节点电荷的测量值达到节点电荷的理论值。 对于电容结构（SCA）的每个节点，该装置还包括用于放电的受控开关（Sres），连接在节点和地之间。 该器件用于控制属于集成电路（IC）的集成电容器，集成电路（IC）位于半导体晶片的区域中，并由切割线划分，其中电容结构插入切割线，电容器框架表面 的电容结构最多等于集成电路电容器的最小表面。 控制方法包括以下步骤：放电所有节点; 所有节点的充电; 测量节点与地面之间的电流表连接; 和电流表断开。
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公开(公告)号：EP1151540A1
公开(公告)日：2001-11-07
申请号：EP00959483.9
申请日：2000-08-28
发明人： MICHEL, Jean-Yves
IPC分类号： H03M1/10
摘要： A circuit arrangement (10, 110) and method for testing the differential non-linearity (DNL) of a digital-to-analog converter (DAC) (20, 120) determines whether the digital-to-analog converter has an analog output (22, 122) that is monotonic, and thus the DAC is functional. The design is appropriate for being implemented on an integrated circuit containing a digital-to-analog converter, creating an efficient self-test circuit arrangement. A counter (12, 112) generates a monotonic sequence of digital input codes for a digital input of the digital-to-analog converter. A monotonicity comparator (24, 24', 24'', 124), such as a one-stage or multistage sample and hold circuit arrangement, detects any non-monotonic transition in the analog output of the digital-to-analog converter, generating an error signal as an output. An output switch, such as a digital flip-flop (37', 37'', 137), may be set by the error signal, for monitoring by other devices. A clock signal synchronizes the counter and the monotonicity comparator. A reset signal may be included to reset the counter to the first digital input code in the sequence. The reset may also reset the output switch.
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公开(公告)号：EP1145442A2
公开(公告)日：2001-10-17
申请号：EP00959482.1
申请日：2000-08-28
发明人： MICHEL, Jean-Yves
IPC分类号： H03M1/10
摘要： A test circuit arrangement (10, 110) and method for functionally testing an analog-to-digital converter (ADC) (12, 112), such as an N-bit ADC, by testing for a missing digital output code. A digital code generator (19, 119), such as including an N-bit word generator or an N-bit counter reset by an M-bit timer, generates a digital output code that is compared with the digital output of the N-bit ADC. The comparison is performed by a missing code detection circuit (20, 120). In response to the comparison, the missing code detection circuit operatively drives, such as by controlling an integrator (24, 124), an analog input of the N-bit ADC toward the desired digital output code. The missing code detection circuit includes an output circuit (23), such as including a flip-flop, wherein a code detected output is set when each desired digital output code is detected in the digital output of the N-bit ADC. Implementation of a test circuit arrangement may include fabrication as a built-in test circuit in an integrated device, such as a semiconductor integrated circuit including the N-bit ADC to be tested.
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