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    MONOLITHIC INTEGRATED CIRCUIT CHIP INTEGRATING MULTIPLE DEVICES
    31.
    发明公开
    MONOLITHIC INTEGRATED CIRCUIT CHIP INTEGRATING MULTIPLE DEVICES 有权
    与多个设备单片集成电路芯片

    公开(公告)号：EP2878009A1

    公开(公告)日：2015-06-03

    申请号：EP13731186.6

    申请日：2013-05-24

    Applicant: Raytheon Company

    Inventor： SAUNDERS, Jeffrey, H.

    IPC: H01L21/8258 ,  H01L27/06 ,  H01L27/085

    CPC classification number: H01L21/8258 ,  G01S7/032 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A monolithic integrated circuit (IC) chip containing a plurality of transistors, including: a substrate; a first transistor on the substrate; and a second transistor integrally formed on the substrate with the first transistor, the second transistor having a different structure than the first transistor, wherein the first transistor includes a first material system and the second transistor includes a second material system different from the first material system. The monolithic IC chip may further include a third transistor integrally formed on the substrate with the first and second transistors. The first transistor may include gallium nitride (GaN) and the second and third transistors may include silicon carbide (SiC).

    STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR
    32.
    发明公开
    STRUCTURE HAVING MONOLITHIC HETEROGENEOUS INTEGRATION OF COMPOUND SEMICONDUCTORS WITH ELEMENTAL SEMICONDUCTOR 审中-公开
    STR UR UR UR R R R R R R R R R R R R R R R R R R R R R R R R R R R R

    公开(公告)号：EP2761649A1

    公开(公告)日：2014-08-06

    申请号：EP12770335.3

    申请日：2012-09-07

    Applicant: Raytheon Company

    Inventor： LAROCHE, Jeffrey, R. ,  KAZIOR, Thomas, E. ,  HOKE, William, E.

    IPC: H01L21/8258 ,  H01L27/12

    Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

    Abstract translation: 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。

    Monolithic integration of silicon and group III-V devices
    34.
    发明公开
    Monolithic integration of silicon and group III-V devices 审中-公开
    硅和III-V器件单片集成

    公开(公告)号：EP2363880A3

    公开(公告)日：2014-01-22

    申请号：EP11001112.9

    申请日：2011-02-11

    Applicant: International Rectifier Corporation

    Inventor： Briere, Michael A.

    IPC: H01L21/8258 ,  H01L27/06 ,  H03K17/567 ,  H03K17/74

    CPC classification number: H01L27/0629 ,  H01L21/8258 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/7786 ,  H03K17/567 ,  H03K17/74

    Abstract: Disclosed is a monolithically integrated silicon and group III-V device that includes a group III-V transistor (228) formed in a III-V semiconductor body disposed over a silicon substrate. At least one via extends through the III-V semiconductor body to couple at least one terminal of the group III-V transistor to a silicon device formed in the silicon substrate. The silicon device can be a Schottky diode (226), and the group III-V transistor can be a GaN HEMT. In one embodiment an anode of the Schottky diode is formed in the silicon substrate. In another embodiment, the anode of the Schottky diode is formed in a lightly doped epitaxial silicon layer (204) atop the silicon substrate. In one embodiment a parallel combination of the Schottky diode and the group III-V transistor is formed, while in another embodiment is series combination is formed.

    Method of manufacturing an integrated semiconductor substrate structure
    36.
    发明公开
    Method of manufacturing an integrated semiconductor substrate structure 有权
    用于集成半导体衬底结构集成半导体衬底结构及其制造方法

    公开(公告)号：EP2317554A1

    公开(公告)日：2011-05-04

    申请号：EP09174721.2

    申请日：2009-10-30

    Applicant: IMEC

    Inventor： Degroote, Stefan ,  Cheng, Kai

    IPC: H01L27/06 ,  H01L21/8252 ,  H01L21/8258

    CPC classification number: H01L27/0605 ,  H01L21/8252 ,  H01L21/8258

    Abstract: The integrated semiconductor substrate structure comprises a substrate (1), a GaN-heterostructure (20) and a semiconductor substrate layer (30). The GaN heterostructure (20) is present in a first device area (51) for definition of GaN-based devices, which heterostructure (20) is covered at least partially with a protection layer (8). The semiconductor substrate layer (30) is present in a second device area (52) for definition of CMOS devices. At least one of the GaN heterostructure (20) and the semiconductor substrate layer (30) is provided in at least one trench (14) in the substrate (1), so that the GaN heterostructure (20) and the semiconductor substrate layer (30) are laterally juxtaposed.

    Abstract translation: 集成的半导体衬底结构包括基板（1），GaN异质结构（20）和半导体层的衬底（30）。 与GaN异质结构（20）存在于第一器件区域（51），用于GaN基器件的定义，异质结构（20）至少部分覆盖有保护层（8）。 半导体基板层（30）存在于CMOS器件的定义中的第二器件区域（52）。 至少与GaN异质结构（20）和半导体基片层（30）中的一个在所述基板（1）设置在至少一个沟槽（14）中，所以没有GaN异质结构（20）和半导体基片层（30 ）的尾盘反弹并列。

    SEMICONDUCTOR DEVICES
    37.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开
    半导体器件

    公开(公告)号：EP1258038A1

    公开(公告)日：2002-11-20

    申请号：EP01907163.8

    申请日：2001-02-08

    Applicant: MOTOROLA, INC.

    Inventor： RAMDANI, Jamal ,  DROOPAD, Ravindranath ,  HILT, Lyndee, L. ,  EISENBEISER, Kurt, William

    IPC: H01L21/8258 ,  H01S5/026 ,  H01L21/20

    CPC classification number: H01S5/0261 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/31691 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/15 ,  H01L33/16 ,  H01L33/30 ,  H01L2924/0002 ,  H01S5/021 ,  H01L2924/00

    Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer (26). Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Semiconductor devices may be formed in both the monocrystalline compound semiconductor layer and the silicon. Semiconductor devices (56, 68, 78, 92) may be formed in both the monocrystalline compound semiconductor layer and the silicon.

    Abstract translation: 通过首先在硅晶片（22）上生长适应缓冲层（24），可以在大硅晶片上生长高质量的化合物半导体材料外延层。 适应缓冲层是由硅氧化物的无定形界面层（28）与硅晶片隔开的单晶氧化物层。 非晶界面层消散应变并允许高质量单晶氧化物容纳缓冲层的生长。 适应缓冲层与下面的硅晶片和上面的单晶化合物半导体层（26）晶格匹配。 适应缓冲层和下面的硅衬底之间的任何晶格失配都由无定形界面层来处理。 半导体器件可以形成在单晶化合物半导体层和硅中。 半导体器件（56,68,78,92）可以形成在单晶化合物半导体层和硅中。

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