公开(公告)号：EP4500245A1

公开(公告)日：2025-02-05

申请号：EP23781587.3

申请日：2023-03-22

Applicant: Taylor, Geoff W.

Inventor： Taylor, Geoff W.

IPC: G02B6/13 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06

公开(公告)号：EP4498422A1

公开(公告)日：2025-01-29

申请号：EP24188563.1

申请日：2024-07-15

Applicant: STMicroelectronics International N.V.

Inventor： DEPETRO, Riccardo

IPC: H01L21/8252 ,  H01L21/761 ,  H01L27/085 ,  H01L21/8258 ,  H01L27/06

Abstract: A semiconductor electronic device (1) is formed in a die (3) having a substrate (15) of semiconductor material of a first conductivity type (P). The device has a first electronic component (5A, 5B) based on heterostructure, which has a body structure (20, 70) of semiconductor material that extending, in the die, on the substrate (15), and an epitaxial multilayer (21, 71) extending in contact with the body structure and having a heterostructure (22, 72). The body structure of the first electronic component has a first doped region (25, 27, 75, 77) of semiconductor material that extends between the heterostructure and the substrate and has a second conductivity type (N) different from the first conductivity type.

公开(公告)号：EP4191656B1

公开(公告)日：2025-01-29

申请号：EP22211028.0

申请日：2022-12-02

Inventor： HUBER, Jonas Emanuel ,  LEONG, Kennith Kin ,  KOLAR, Johann Walter

IPC: H01L21/8258 ,  H01L27/06 ,  H01L29/76 ,  H03K17/72 ,  H03K17/06

公开(公告)号：EP3345209B1

公开(公告)日：2024-07-17

申请号：EP16842434.9

申请日：2016-08-31

IPC: H01L23/31 ,  H01L21/8258

CPC classification number: H01L23/3185 ,  H01L29/00 ,  H01L21/8258

公开(公告)号：EP4391041A1

公开(公告)日：2024-06-26

申请号：EP23209981.2

申请日：2023-11-15

Applicant: Analog Devices, Inc.

Inventor： FIORENZA, James ,  PIEDRA, Daniel

IPC: H01L21/8258 ,  H01L27/06 ,  H01L29/778 ,  H01L29/861 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L21/8258 ,  H01L27/0688 ,  H01L27/0629 ,  H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/8611

Abstract: Techniques to integrate a p-n diode in a substrate below a GaN HEMT, such as in a silicon carbide (SiC) substrate. The p-n diode provides avalanche robustness to the device and over voltage protection to the transistor.

公开(公告)号：EP4210088A1

公开(公告)日：2023-07-12

申请号：EP22197904.0

申请日：2022-09-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： HAZBUN, Ramsey ,  LEVY, Mark ,  Joseph, Alvin ,  ADUSUMILLI, Siva P.

IPC: H01L21/02 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/778 ,  H01L27/088 ,  H01L21/336

Abstract: A structure comprising: a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface, the top surface having a first surface normal, and the faceted surface having a second surface normal that is inclined relative to the first surface normal; a layer stack positioned on the faceted surface of the first semiconductor layer, the layer stack including a plurality of second semiconductor layers, and each second semiconductor layer comprised of a compound semiconductor material; a silicon-based device on the top surface of the first semiconductor layer; and a first compound-semiconductor-based device on the layer stack.

公开(公告)号：EP4203001A1

公开(公告)日：2023-06-28

申请号：EP22205718.4

申请日：2022-11-07

Applicant: Intel Corporation

Inventor： RADOSAVLJEVIC, Marko ,  THEN, Han ,  DASGUPTA, Sansaptak ,  FISCHER, Paul ,  JUN, Kimin ,  MUELLER, Brennen

IPC: H01L21/8258 ,  H01L27/085 ,  H01L27/092 ,  H01L29/778

Abstract: In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.

公开(公告)号：EP4141921A2

公开(公告)日：2023-03-01

申请号：EP22186480.4

申请日：2022-07-22

Applicant: INTEL Corporation

Inventor： RADOSAVLJEVIC, Marko ,  JUN, Kimin ,  THEN, Han Wui ,  FISCHER, Paul ,  THOMAS, Nicole ,  NORDEEN, Paul ,  HOFF, Thomas ,  KOIRALA, Pratik ,  TALUKDAR, Tushar

IPC: H01L21/8258 ,  H01L21/02 ,  H01L27/085 ,  H01L27/06

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer (106B) including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins (104) including silicon. A device layer (108) is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：EP3008752B1

公开(公告)日：2021-04-14

申请号：EP14728394.9

申请日：2014-05-13

Inventor： COMEAU, Jonathan P. ,  LAROCHE, Jeffrey R. ,  BETTENCOURT, John P.

IPC: H01L21/8258 ,  H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/085

公开(公告)号：EP3690928A1

公开(公告)日：2020-08-05

申请号：EP20154416.0

申请日：2020-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： PATTI, Davide Giuseppe

IPC: H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/085

Abstract: The power device is formed by a D-mode HEMT (2) and by a MOSFET (3) in cascade to each other and integrated in a chip (51) having a base body (16) and a heterostructure layer (17) on the base body. The D-mode HEMT (2) comprises a channel area formed in the heterostructure layer; the MOSFET (3) comprises a first and a second conduction region (20, 21) formed in the base body, and an insulated-gate region (33A, 33B) formed in the heterostructure layer, laterally and electrically insulated from the D-mode HEMT. A first metal region (25) extends through the heterostructure layer, laterally to the channel area and in electrical contact with the channel area and the first conduction region (20).