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41.发明公开Apparatus and method for performing a shift operation in a multiplier array circuit 失效装置以及用于执行换档操作到乘法器电路的方法。
公开(公告)号：EP0291356A2
公开(公告)日：1988-11-17
申请号：EP88304420.8
申请日：1988-05-16
CPC分类号： G06F7/4876 , G06F5/012 , G06F7/49947
摘要： In floating point opertaions, it is necessary to align the fractions of the exponents before addition or subtraction operations can be executed. This fraction alignment is performed by a shifting operation, typically using dedicated apparatus such as a barrel shifter. While the dedicated apparatus provides high performance in the execution of the shifting operation, this performance is accomplished by reserving a portion of the substrate area to apparatus implementation. To avoid the use of dedicated apparatus, the shifting operation is performed in a multiplier unit, according to the present invention, by entering the number to be shifted in the multiplicand register of the multiplier unit while entering appropriate control signals in the multiplier register. In this manner, a shifting operation can be performed without dedicated apparatus and with minor impact on performance.
摘要翻译： 在浮点opertaions，有必要以对准指数的级分之前加法或减法运算可以被执行。 该馏分对准是通过换档操作，典型地使用专用装置执行：诸如桶式移位器。 虽然专用装置在换档操作的执行提供了高性能，这种性能是通过保留在基板区域的一部分的装置的实施来实现。 为了避免使用专用装置，换档操作被在乘法器单元执行，雅鼎在本发明中，通过输入号码进行在乘法器单元的被乘数寄存器中，而在乘法器寄存器输入适当的控制信号移位。 以这种方式，换档操作可以在没有专用设备和对性能影响较小来进行。
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公开(公告)号：EP0233635A2
公开(公告)日：1987-08-26
申请号：EP87102242.2
申请日：1987-02-17
申请人： NEC CORPORATION
发明人： Nukiyama, Tomoji
IPC分类号： G06F5/00
摘要： A shift control circuit comprising an arithmetic circuit (20) for producing a string of a predetermined number of data bits, a logic circuit (22) for detecting the positive or negative sign of the bit string and producing a first switch signal responsive to the positive sign of the bit string or a second switch signal responsive to the negative sign of the bit string, a ones complement generator circuit (24) for producing a signal representative of the ones complement of the bit string, a first selective signal transfer circuit (26) such as a multiplexer which is transparent directly to the bit string in response to the first switch signal or to the signal from the ones complement generator circuit in response to the second switch signal, a decoder circuit (28) for decording the bit string or the signal passed through the first selective signal transfer circuit for producing a decoded output signal, a single-bit shifter circuit (30) for shifting the bit of the decoded output signal by a single bit in a predetermined direction for producing a single-bit shifted output signal, and a second selective signal transfer circuit (32) such as a multiplexer which is transparent directly to the decoded output signal in response to the first switch signal or to the signal from the single-bit shifter circuit (30) in response to the second switch signal.
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公开(公告)号：EP0182963A2
公开(公告)日：1986-06-04
申请号：EP85107059.9
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： In a digital signal processor comprising interface means for data input output with an external device; data buses (21, 22); data memories (5, 6); floating point multiplier (14) for adding exponent parts and multiplying mantissa parts of a pair of data applied; a floating adder/subtracter (15); an accumulator (16); a switching circuit (17) and a control circuit (4), the floating adder/subtracter comprising adjusting means (67 to 69, 63 to 65) for adjusting two floating point data; an adder (75) for adding the two adjusted mantissa parts of the two floating point data; a leftwards shift circuit (76) for shifting output data from the adder; a zero detector (79) to provide a first shift data signal; a correction circuit (85) and a control circuit (89) to generate an underflow signal and provide a normalized exponent part of the sum of the two data; a constant adder circuit (77) and a selector (81) for providing the shift circuit with a second shift data signal, or the first shift data signal depending on whether or not the underflow signal is generated.
摘要翻译： 一种数字信号处理器，包括用于与外部设备进行数据输入/输出的接口装置; 数据总线（21,22）; 数据存储器（5,6）; 浮点乘数（14），用于添加指数部分和乘以一对数据的尾数部分; 浮动加法器/减法器（15）; 蓄能器（16）; 开关电路（17）和控制电路（4），所述浮动加法器/减法器包括用于调整两个浮点数据的调整装置（67至69,63至65） 加法器（75），用于将两个浮点数据的两个经调整的尾数部分相加; 用于从加法器移位输出数据的左移位电路（76） 零检测器（79），用于提供第一移位数据信号; 校正电路（85）和控制电路（89），用于产生下溢信号并提供两个数据之和的归一化指数部分; 用于向移位电路提供第二移位数据信号的恒定加法器电路（77）和选择器（81），或根据是否产生下溢信号的第一移位数据信号。
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公开(公告)号：EP0051422A3
公开(公告)日：1982-12-01
申请号：EP81305062
申请日：1981-10-27
发明人： Hagiwara, Yoshimune , Sugiyama, Shizuo , Maeda, Narimichi , Yumoto, Osamu , Akazawa, Takashi , Kobayashi, Masahito , Kita, Yasuhiro , Kita, Yuzo
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F7/49921 , G06F2207/3856
摘要： A digital signal processor comprising interface means for data inputoutput with an external device; a first data bus (21) which has a predetermined number of bits and which is connected to the interface means; data memories (5, 6) connected to the data bus; a second data bus (22) onto which a data from the data memories is read out; a floating point multiplier (14) connected with the first and second data buses and for adding exponent parts and multiplying mantissa parts of a pair of data applied, to deliver an operated result having a number of bits larger than that of the first data bus; a floating adder-subtracter (15) including an input selection portion selecting a pair of data appointed by a program instruction from amongst a plurality of data containing the output of the multiplier, and for adding subtracting said pair of data; an accumulator (16) for holding a data delivered from the adder subtracter and having a number of bits larger than that of the first data bus; a third data bus (27) which has a number of bits larger than that of the first data bus and which supplies an output of said accumulator to said input selection portion of said adder subtracter; a switching circuit (17) connected between said accumulator and the first data bus and for reducing the number of bits of the output data of the accumulator and then supplying the resultant data to the first data bus; and a control circuit (4) for controlling the operations of the respective means in accordance with program instructions.
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公开(公告)号：EP2846257B1
公开(公告)日：2017-08-09
申请号：EP14182740.2
申请日：2014-08-29
申请人： Altera Corporation
发明人： Czajkowski, Tomasz
CPC分类号： G06F7/485 , G06F5/012 , G06F7/49915 , G06F17/10 , G06F2207/483
摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.
摘要翻译： 提供集成电路，其执行涉及至少三个浮点数的浮点加法或减法操作。 通过动态扩展尾数位数，确定具有最大指数的浮点数，并将其他浮点数的尾数向右移位，来对浮点数进行预处理。 每个扩展后尾数至少有两次进入浮点运算的尾数位数。 确切的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数都向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差值。
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46.发明授权
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公开(公告)号：EP2409219A1
公开(公告)日：2012-01-25
申请号：EP10710952.2
申请日：2010-03-11
发明人： OLIVER, David, S.
摘要： A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a shift value corresponding to a number of bit positions to shift the second mantissa such that the second exponent value is the same as the first exponent value. The alignment shifter may detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value. The selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit.
摘要翻译： 浮点单元包括浮点加法器，用于在具有指数和尾数的第一和第二浮点数之间执行浮点加法运算。 浮点单元还包括对准移位器，其可以计算对应于多个位位置的移位值，以移位第二尾数，使得第二指数值与第一指数值相同。 对准移位器可以检测偏移条件，其中移位值大于或等于选择的过渡阈值。 所选择的过冲阈值包括包括最小超越阈值和最大超越阈值在内的超值值范围内的基数2，并且具有从最低有效位开始为零的连续比特的最大数目。
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公开(公告)号：EP1806652A3
公开(公告)日：2008-11-05
申请号：EP06251769.3
申请日：2006-03-30
申请人： Fujitsu Ltd.
CPC分类号： G06F5/012 , G06F7/483 , G06F7/49952 , G06F7/49957 , G06F7/5443 , G06F7/74 , G06F2207/382
摘要： An arithmetic operation unit, which generates shift information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit for outputting the arithmetic operation result, a normalizer (30) having a plurality of shifters for normalizing the arithmetic operation result, a shift amount calculator for calculating a plurality of shift amounts for the plural shifters, and a predictor (51) for generating interim information that is a result of prediction of whether or not the arithmetic operation result is to be shifted when the arithmetic operation result is normalized, by using the plural shift amounts, and a generator (52) for generating the shift information by using the interim information. The cycle time required to generate the interim information (a sticky bit) is shortened to efficiently generate the sticky bit, and the hardware resources for generating the sticky bit are reduced.
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公开(公告)号：EP1429244A1
公开(公告)日：2004-06-16
申请号：EP02800700.3
申请日：2002-09-17
发明人： KOBAYASHI, Shiro
摘要： To provide a compiler apparatus which makes it easy to describe arithmetic operations in source programs, makes it simple to write source programs, and reduces bugs, when performing block floating-point operations in software.
When the compiler apparatus is fed a source program containing computing expressions written using block floating variables, it detects computing expressions for addition in the source program, expands that part of the detected computing expressions which involves addition into instruction codes which specify addition for data blocks corresponding to a plurality of block floating variables to be subjected to addition, embeds the instruction codes in the object program to be generated, and outputs the object program.摘要翻译： 为了提供一种使源代码程序中的算术运算易于描述的编译器，在软件中执行块浮点运算时，可以很容易地编写源程序，并减少错误。 当编译器装置被馈送包含使用块浮动变量写入的计算表达式的源程序时，它检测源程序中的加法计算表达式，将检测到的计算表达式的那部分扩展到指定加法的指令代码中 对于与要进行加法的多个块浮动变量相对应的数据块，将指令代码嵌入到要生成的对象程序中，并输出目标程序。
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50.发明公开Method and system for executing operations on denormalised numbers 审中-公开Verfahren und System zurAusführungvon Operationen auf denormalisierten Zahlen
公开(公告)号：EP0901067A2
公开(公告)日：1999-03-10
申请号：EP98306442.9
申请日：1998-08-12
发明人： Schwarz, Eric Mark , Giamei, Bruce , Krygowski, Christopher , Check, Mark Anthony , Liptay, John Stephen
IPC分类号： G06F5/01
CPC分类号： G06F5/012 , G06F9/3861 , G06F9/3875 , G06F2207/3884
摘要： A method and system for processing instructions in a floating point unit for executing denormalized numbers in floating point pipeline via serializing uses an instruction unit and having a control unit and a pipelined data flow unit, a shifter and a rounding unit. The floating point unit has an external feedback path for providing intermediate result data from said rounding unit to an input of the pipelined data flow unit to reuse the pipeline for denormalization by passing intermediate results in the pipeline which have a denormalized condition computed after the exponent calculation of the shifting circuit directly from the rounding unit to the top of the dataflow in the pipeline via an external feedback path. The pipelined has two paths which are selected based on the presence of other instructions in the pipeline. If no other instructions are in the pipeline a first path is taken which uses the external feedback path from the rounding unit back into the top of the dataflow. When there are instructions in the pipeline a shifter unit performing normalization of the fraction indicates possible underflow of the exponent, and prepares to hold the exponent and the fraction in a floating point data flow register; and upon detection of exponent underflow during the rounder stage and detection of any other instructions in pipeline; then the control unit forces an interrupt for serialization, and cancels execution of this instruction and other instructions in pipeline.
摘要翻译： 用于处理浮点单元中的指令的方法和系统，用于通过串行化来执行浮点流水线中的非规范化数字，使用指令单元并具有控制单元和流水线数据流单元，移位器和舍入单元。 浮点单元具有用于将来自所述四舍五入单元的中间结果数据提供给流水线数据流单元的输入的外部反馈路径，以通过将具有在指数计算之后计算的非归一化状态的流水线中的中间结果重新使用来进行非规范化 的移位电路通过外部反馈路径直接从舍入单元到流水线中的数据流的顶部。 流水线有两条路径，这些路径是根据流水线中其他指令的存在而选择的。 如果没有其他指令在流水线中，则采用第一路径，其使用从舍入单元返回到数据流的顶部的外部反馈路径。 当在流水线中存在指令时，执行分数的归一化的移位单元指示指数的可能下溢，并准备保持指数和分数在浮点数据流寄存器中; 并在检测到倒圆阶段期间的指数下溢和检测管道中的任何其他指令时; 那么控制单元强制中断进行串行化，并取消执行该指令和其他指令。
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