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    VECTOR PROCESSING ENGINE EMPLOYING FORMAT CONVERSION CIRCUITRY IN DATA FLOW PATHS BETWEEN VECTOR DATA MEMORY AND EXECUTION UNITS, AND RELATED METHOD
    41.
    发明公开
    VECTOR PROCESSING ENGINE EMPLOYING FORMAT CONVERSION CIRCUITRY IN DATA FLOW PATHS BETWEEN VECTOR DATA MEMORY AND EXECUTION UNITS, AND RELATED METHOD 审中-公开
    在它们之间向量资料存储和执行单元和相应的方法处理数据流格式转换电路矢量处理机

    公开(公告)号：EP3069232A1

    公开(公告)日：2016-09-21

    申请号：EP14806777.0

    申请日：2014-11-12

    申请人： Qualcomm Incorporated

    发明人： KHAN, Raheel

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/80

    CPC分类号： G06F9/30181 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8076

    摘要： Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

    DYNAMICALLY ERECTABLE COMPUTER SYSTEM
    42.
    发明公开
    DYNAMICALLY ERECTABLE COMPUTER SYSTEM 有权
    动态部署计算机系统

    公开(公告)号：EP2856313A4

    公开(公告)日：2016-03-02

    申请号：EP13793168

    申请日：2013-05-23

    申请人： SMITH ROGER

    发明人： SMITH ROGER

    IPC分类号： G06F11/07 ,  G06F11/14 ,  G06F11/20

    CPC分类号： G06F15/825 ,  G06F7/76 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/2002 ,  G06F12/0875 ,  G06F15/76 ,  G06F2015/765 ,  G06F2212/452

    摘要： A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.

    MULTIPLICATION DE MATRICES DE BITS UTILISANT DES REGISTRES EXPLICITES
    43.
    发明公开
    MULTIPLICATION DE MATRICES DE BITS UTILISANT DES REGISTRES EXPLICITES 审中-公开
    钻头倍增模具使用快速寄存器

    公开(公告)号：EP2947562A1

    公开(公告)日：2015-11-25

    申请号：EP15167989.1

    申请日：2015-05-18

    申请人： Kalray

    发明人： Dupont de Dinechin, Benoît ,  Rybczynska, Marta

    IPC分类号： G06F9/30

    CPC分类号： G06F7/523 ,  G06F7/76 ,  G06F7/78 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F17/16

    摘要： L'invention est relative à un processeur comprenant, dans son jeu d'instructions, une instruction ( sbmm ) de multiplication de matrices de bits ayant un premier opérande (A) de précision double représentant une première matrice à multiplier, un deuxième opérande (B) désignant explicitement deux registres de travail quelconques de précision simple dont les contenus joints représentent une deuxième matrice à multiplier, et un paramètre de destination (C) désignant explicitement deux registres de travail quelconques de précision simple pour contenir conjointement une matrice représentant le résultat de la multiplication.

    Damping apparatus for reducing vibration of automobile body
    47.
    发明公开
    Damping apparatus for reducing vibration of automobile body 有权
    Dämpfvorrichtungzur Reduktion der Schwingungen der Karosserie eines Kraftfahrzeugs

    公开(公告)号：EP2072852A2

    公开(公告)日：2009-06-24

    申请号：EP08075933.5

    申请日：2007-04-27

    申请人： Shinko Electric Co., Ltd

    发明人： Moriya, Hideaki ,  Muragishi, Yasushi ,  Sato, Yushi ,  Fukunaga, Takashi ,  Nakano, Katsuyoshi ,  Nakagawa, Hiroshi ,  Fujii, Takayoshi ,  Onoue, Takashi ,  Narihisa, Masaaki

    IPC分类号： F16F7/10

    CPC分类号： F16F7/1005 ,  B60G17/018 ,  F16F15/002 ,  G05D19/02 ,  G06F7/76

    摘要： An object of the present invention is to provide a damping apparatus for an automobile, capable of ensuring a high level of reliability while obtaining an excellent damping effect with a simple configuration. The damping apparatus for an automobile that reduces vibrations of an automobile body, includes: an actuator that is attached to the automobile body and drives an auxiliary mass; a current detector that detects a current flowing through an armature of the actuator; a section that detects a terminal voltage applied to the actuator; a calculation circuit that calculates an induced voltage of the actuator, and further calculates at least one of the relative velocity, relative displacement, and relative acceleration of the actuator, based on a current detected by the current detector and the terminal voltage; and a control circuit that drive-controls the actuator based on at least one of the relative velocity, relative displacement, and relative acceleration of the actuator calculated by the calculation circuit.

    摘要翻译： 本发明的目的是提供一种用于汽车的阻尼装置，其能够以简单的构造获得优异的阻尼效果，从而确保高可靠性。 一种减轻汽车车体振动的汽车减震装置，具备：安装在汽车车体上并驱动辅助车体的致动器; 电流检测器，其检测流过致动器的电枢的电流; 检测施加到致动器的端子电压的部分; 计算所述致动器的感应电压的计算电路，并且基于由所述电流检测器检测出的电流和所述端子电压，进一步计算所述致动器的相对速度，相对位移和相对加速度中的至少一个; 以及控制电路，其基于由所述计算电路计算出的所述致动器的相对速度，相对位移和相对加速度中的至少一个来驱动所述致动器。

    Extending a repetition period of a random sequence
    48.
    发明公开
    Extending a repetition period of a random sequence 有权
    Verlängerungeiner Wiederholungsperiode einer Zufallssequenz

    公开(公告)号：EP2000900A2

    公开(公告)日：2008-12-10

    申请号：EP08009383.4

    申请日：2008-05-21

    申请人： Harris Corporation

    发明人： Michaels, Alan J.

    IPC分类号： G06F7/58 ,  G06F7/72

    CPC分类号： G06F7/582 ,  G06F7/729 ,  G06F7/76

    摘要： A method is provided for extending a sequence repetition period of a random number generator in systems based on the availability of random sequences. The method includes performing RNS arithmetic operations to express a random number in a sequence as RNS residue values. Each generated random number has a value between zero and n!-1. The method also includes converting each of the RNS residue values to a relatively prime base number system so that each of the RNS residue values includes at least one digit. The method further includes generating an arbitrary permutation ordering of output sequence numbers using a select combination of digits associated with each of the RNS residue values. The arbitrary permutation ordering is applied to a cyclic structure having n elements. Each of the n elements has an associated output sequence number.

    摘要翻译： 提供了一种基于随机序列的可用性在系统中扩展随机数发生器的序列重复周期的方法。 该方法包括执行RNS算术运算以将序列中的随机数表示为RNS残差值。 每个生成的随机数都具有零和n！-1之间的值。 该方法还包括将RNS残留值中的每一个转换为相对主要的基数系统，使得每个RNS残留值包括至少一个数字。 该方法还包括使用与每个RNS残差值相关联的数字的选择组合来产生输出序列号的任意排列顺序。 任意排列顺序被应用于具有n个元素的循环结构。 n个元素中的每一个都具有相关的输出序列号。