公开(公告)号：EP0547241A1

公开(公告)日：1993-06-23

申请号：EP92914387.0

申请日：1992-07-07

Applicant: SEIKO EPSON CORPORATION

Inventor： NGUYEN, Le Trong ,  LENTZ, Derek, J. ,  MIYAYAMA, Yoshiyuki ,  GARG, Sanjiv ,  HAGIWARA, Yasuaki ,  WANG, Johannes ,  LAU, Tei-Li ,  TRANG, Quang, H.

IPC: G06F9

CPC classification number: G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

Abstract: L'architecture de microprocesseur RISC, basée sur une mémoire centrale et à performances élevées, permet d'exécuter simultanément des instructions obtenues de la mémoire par l'intermédiaire d'une unité d'extraction d'instructions comprenant des parcours d'extractions multiples permettant l'extraction d'une suite d'instructions de programme principal, d'une suite d'instructions de branchement conditionnel cible et d'une suite d'instructions de procédure. La trajectoire d'extraction de branchement conditionnel cible permet d'extraire les deux suites d'instructions possibles pour une instruction de branchement conditionnel. La trajectoire d'extraction d'instructions de procédure permet d'accéder à une suite d'instructions supplémentaires sans remettre à zéro les tampons d'extraction principaux ou cibles. Chaque ensemble d'instruction comprend une multiplicité d'instructions de longueur fixe. Un système premier entré-premier sorti pour les instructions est prévu afin de mettre en mémoire tampon des ensembles d'instructions dans une multiplicité de tampons d'ensembles d'instructions comprenant un premier et un second tampon. Une unité d'exécution d'instructions comprenant un fichier de registre et une multiplicité d'unités fonctionnelles est pourvue d'une unité de commande d'instructions pouvant examiner les ensembles d'instructions dans les premier et second tampons et organiser n'importe quelle instruction afin qu'elle soit exécutée par des unités fonctionnelles disponibles. Des trajectoires de données multiples entre les unités fonctionnelles et le fichier de registre permettent aux unités fonctionnelles d'obtenir des accès multiples et indépendants au fichier de registre tel qu'il est requis pour l'exécution des instructions respectives.

公开(公告)号：EP0528695A2

公开(公告)日：1993-02-24

申请号：EP92307632.7

申请日：1992-08-20

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Matsuzaki, Toshimichi ,  Deguchi, Masashi

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181

Abstract: Disclosed is a data processing apparatus comprising a decode device for decoding an instruction code including an operation code and two register designation codes and an instruction execution device for executing appropriate process according to the results decoded by the decode device, wherein the instruction execution device executes a first process when the two register designation codes are different from each other and executes a second process when they are equal.

Abstract translation: 公开了一种数据处理装置，包括：解码装置，用于对包括操作码和两个寄存器指定码的指令码进行解码，以及用于根据由解码装置解码的结果执行适当处理的指令执行装置，其中指令执行装置执行 当两个寄存器指定码彼此不同时执行第一处理，并且当它们相等时执行第二处理。

公开(公告)号：EP0352082A3

公开(公告)日：1993-01-07

申请号：EP89307295.9

申请日：1989-07-19

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Grundmann, William J. ,  Madden, William C. ,  Uhler, George M.

IPC: G06F9/26 ,  G06F7/00

CPC classification number: G06F7/785 ,  G06F9/26 ,  G06F9/265 ,  G06F9/30134

Abstract: A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An uncondi­tional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the micro­instruction does not prevent completion of the stack operation in one machine cycle.

公开(公告)号：EP0154529B1

公开(公告)日：1992-09-09

申请号：EP85301420.7

申请日：1985-03-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Candy, Donald W. ,  Ott, Granville E.

IPC: G06F9/44

CPC classification number: G06F9/3017 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/45504

公开(公告)号：EP0399762A3

公开(公告)日：1992-01-22

申请号：EP90305489.8

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W.

IPC: G06F9/38

CPC classification number: G06F9/30134 ,  G06F9/261 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3853 ,  G06F9/3861

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

公开(公告)号：EP0399762A2

公开(公告)日：1990-11-28

申请号：EP90305489.8

申请日：1990-05-21

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Horst, Robert W.

IPC: G06F9/38

CPC classification number: G06F9/30134 ,  G06F9/261 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3844 ,  G06F9/3853 ,  G06F9/3861

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract translation: 用于在单个时钟期间发出指令系列的系统包括解码器，用于响应于解码结果对指令和逻辑系列进行解码，以确定如果在一个时钟期间发出家庭资源冲突将发生。 如果没有发生资源冲突，则执行单元执行该系列，而不考虑该系列中的指令之间是否存在相关性。

公开(公告)号：EP0352082A2

公开(公告)日：1990-01-24

申请号：EP89307295.9

申请日：1989-07-19

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Grundmann, William J. ,  Madden, William C. ,  Uhler, George M.

IPC: G06F9/26 ,  G06F7/00

CPC classification number: G06F7/785 ,  G06F9/26 ,  G06F9/265 ,  G06F9/30134

Abstract: A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An uncondi­tional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the micro­instruction does not prevent completion of the stack operation in one machine cycle.

Abstract translation: 用于存储流水线CPU中的微指令地址的存储器堆栈被构建为使用堆栈指针的先进先出存储器，其将读控制应用于堆栈的一个位置，并将写控制应用于下一较高位置。 每个机器周期执行无条件的读写操作，在微指令可以被解码之前，然后使用读总线上的数据或来自写总线的数据，并且如果堆栈Push或Pop被解码，则指针被递增或递减 。 这些对应于呼叫或返回微指令。 因此，解码微指令的延迟并不能防止在一个机器周期中完成堆栈操作。

公开(公告)号：EP0101718B1

公开(公告)日：1986-05-07

申请号：EP83901027.9

申请日：1983-02-15

Applicant: Western Electric Company, Incorporated

Inventor： DITZEL, David Roger ,  McLELLAN, Hubert Rae, Jr.

IPC: G06F9/42

CPC classification number: G06F9/30134 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/4486 ,  G06F2212/451

Abstract: The local variables of procedures are automatically mapped form main memory of a computer into a circular buffer comprising machine registers. As instructions are fetched from the main memory, the instructions are partially decoded by adding the stack pointer to the offset and then stored in an instruction cache. In cases where the sum of the memory locations required by the procedures exceed available register memory, the contents of the registers nearest the maximum stack pointer are flushed back to main memory.

公开(公告)号：EP0154529A2

公开(公告)日：1985-09-11

申请号：EP85301420.7

申请日：1985-03-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Candy, Donald W. ,  Ott, Granville E.

IPC: G06F9/44

CPC classification number: G06F9/3017 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/45504

Abstract: A threaded interpretive processor includes an input/ output (I/O) bus (10) and an address bus (12) for carrying data thereon. An internal ROM/RAM (80) is interfaced with the I/O bus (10) and is addressable from the address bus (12). Instructions placed on the I/O bus (10) are clocked onto the address bus (12) through an instruction pointer (86) in response to a system dock. The data on the I/O bus (10) is also clocked to a microcode ROM (60) through an instruction register (58). The microcode ROM (60) outputs microcode instructions to control the system operation. The microcode instructions control a parameter stack. The parameter stack consists of an eight register rotary stack (44) that has the outputs thereof simultaneously accessable by two output buses (46) and (48) and the inputs thereof accessable by an interface bus (36) and a data input bus (50). The outputs of the rotary stack (44) are input to an arithmetic logic unit (16), the output of which is input back into the rotary stack (44). Transfer gates are provided to control data flow on the output buses and input buses such that the data in the rotary stack (44) can be manipulated. Addresses of microcode instructions are sequentially placed onto I/O bus (10) for controlling the microcode ROM (60) and the instruction pointer (86) increments this instruction address to select the next sequential instruction address. In this manner, instructions can be sequentially executed in sequential clock cycles.

公开(公告)号：EP4428758A1

公开(公告)日：2024-09-11

申请号：EP24162272.9

申请日：2024-03-08

Applicant: Beijing Horizon Information Technology Co., Ltd.

Inventor： HE, Yibo ,  XIAO, Lei ,  TAN, Honghe

IPC: G06N3/063 ,  G06F9/50 ,  G06F9/54 ,  G06N3/045 ,  G06F9/30

CPC classification number: Y02D10/00 ,  G06N3/063 ,  G06F2209/50920130101 ,  G06F2209/501720130101 ,  G06F9/5066 ,  G06F9/544 ,  G06N3/045 ,  G06F9/30134 ,  G06N3/04

Abstract: Disclosed are a method and apparatus for processing neural network feature map using a plurality of accelerators. The method includes: reading first feature data about the neural network feature map from first shift register array in first accelerator among a plurality of neural network accelerators, and first weight data corresponding to the first feature data from first buffer; performing preset operation on the first feature data and first weight data using the first accelerator, to obtain a first operation result; shifting, according to preset shift rule, first overlapping feature data in the first feature data and required by a second accelerator to a second shift register array of the second accelerator; and performing a preset operation on the second feature data from the second shift register array including the first overlapping feature data and the read second weight data using the second accelerator, to obtain a second operation result.