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    SEMICONDUCTOR MEMORY DEVICE
    42.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：EP0452510A4

    公开(公告)日：1992-04-29

    申请号：EP90916367

    申请日：1990-11-07

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： KAWAMOTO, SATORU SEJURUSIBATA A-101

    IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/34

    CPC分类号： G11C11/4076 ,  G11C8/18

    摘要： An address multiplex type of semiconductor memory device which allows access at a higher speed. It is provided with a first timing circuit (1) for detecting the timing at which a row address strobe signal is activated to output a first timing signal, a second timing circuit (1) for detecting the timing at which the row address strobe signal changes from the activated state to a non-activated state to output a second timing signal, an address change detection circuit for detecting a change in the contents of the row address signal between the first timing signal and the second timing signal to output an address change signal, a row decoder (13) for decoding the contents of the row address signal in accordance with the first timing signal and for decoding the contents of the row address signal in accordance with the second timing signal when the address change signal is outputted, and a word driver (14) for activating word lines decoded in accordance with the second timing signal. This device is applied to dynamic random access memories.

    摘要翻译： 地址多路复用型半导体存储器装置，允许以更高的速度访问。 它提供有：第一定时电路（1），用于检测行地址选通信号被激活以输出第一定时信号的定时;第二定时电路（1），用于检测行地址选通信号改变的定时 从激活状态转换到非激活状态以输出第二定时信号;地址改变检测电路，用于检测第一定时信号和第二定时信号之间的行地址信号的内容的改变，以输出地址改变信号 行译码器（13），用于根据第一定时信号对行地址信号的内容进行译码，并在输出地址改变信号时根据第二定时信号译码行地址信号的内容;以及a 字驱动器（14），用于激活根据第二定时信号解码的字线。 该器件应用于动态随机存取存储器。

    MEMORY ARCHITECTURE
    48.
    发明公开
    MEMORY ARCHITECTURE 审中-公开

    公开(公告)号：EP3937173A1

    公开(公告)日：2022-01-12

    申请号：EP21184730.6

    申请日：2021-07-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd

    发明人： JAIN, Sanjeev Kumar

    IPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C5/02 ,  G11C7/10 ,  G11C7/22

    摘要： Systems and method are provided for a memory circuit. A predecoder circuit is configured to receive a first address signal, a first clock signal, and a second clock signal. The predecoder circuit is configured to generate a selection signal based on the first clock signal and the first address signal. And the predecoder circuit is further configured to maintain the selection signal based on the second clock signal and the first address signal.

    TIMING CONTROL IN A QUANTUM MEMORY SYSTEM
    49.
    发明公开
    TIMING CONTROL IN A QUANTUM MEMORY SYSTEM 审中-公开

    公开(公告)号：EP3872812A1

    公开(公告)日：2021-09-01

    申请号：EP21163890.3

    申请日：2016-02-26

    申请人： Northrop Grumman Systems Corporation

    发明人： Reohr, William Robert ,  Shauck, Steven Brian ,  Miller, Donald Lynn ,  Horner, Jeremy William ,  Josephsen, Nathan Trent

    IPC分类号： G11C11/44 ,  G11C7/22 ,  G11C7/12 ,  H01F6/00 ,  G11C8/04 ,  G11C8/18 ,  H01L39/22 ,  G11C11/16

    摘要： One embodiment describes a quantum memory system (10, 16, 50). The system includes a plurality of quantum memory cells (102) arranged in an array of rows and columns. Each of the plurality of quantum memory cells (102) can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller (20, 450) comprising a plurality of flux pumps (24, 56, 58) configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals (REQ) based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.