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公开(公告)号：EP4210099A1
公开(公告)日：2023-07-12
申请号：EP22209061.5
申请日：2022-11-23
申请人： Intel Corporation
发明人： LI, Xiang , VERGIS, George , MCCALL, James A.
IPC分类号： H01L23/498 , H01L23/66 , H01L23/552
摘要： An integrated circuit package includes a substrate with traces for high speed communication that are subject to crosstalk. The traces include overlapping pads on different layers of the substrate, which can increase the mutual capacitance of the signal lines, which will offset the mutual inductance. Thus, the overlapping pads can reduce the crosstalk between the signal traces.
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2.发明公开
公开(公告)号：EP3651154A1
公开(公告)日：2020-05-13
申请号：EP19217490.2
申请日：2013-11-22
申请人： INTEL Corporation
发明人： VERGIS, George , BAINS, Kuljit S. , MCCALL, James A. , CHANG, Ge
IPC分类号： G11C11/40
摘要： Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.
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公开(公告)号：EP3014772A1
公开(公告)日：2016-05-04
申请号：EP14818656.2
申请日：2014-06-19
申请人： Intel Corporation
IPC分类号： H03K19/0175 , H04L25/02
CPC分类号： H02M3/158 , G11C7/1057 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/105 , H04L25/0276 , H04L25/029
摘要： A transmission line interface circuit includes a voltage regulator to control a voltage swing of the transmission line interface circuit for signal transmission. The transmission line interface circuit includes complementary driver elements, including a p-type driver element to pull up the transmission line in response to a logic high, and an n-type driver element to pull down the transmission line in response to a logic low. The voltage regulator is coupled between one of the driver elements and a respective voltage reference to reduce a voltage swing of the transmission line interface circuit.
摘要翻译： 传输线接口电路包括用于控制用于信号传输的传输线接口电路的电压摆幅的电压调节器。 传输线接口电路包括互补驱动器元件，包括用于响应于逻辑高来上拉传输线的p型驱动元件，以及n型驱动器元件，用于响应于逻辑低来拉低传输线。 电压调节器耦合在驱动器元件之一和相应的电压基准之间以减小传输线接口电路的电压摆幅。
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公开(公告)号：EP4238094A1
公开(公告)日：2023-09-06
申请号：EP21887139.0
申请日：2021-09-21
申请人： INTEL Corporation
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公开(公告)号：EP3304326A1
公开(公告)日：2018-04-11
申请号：EP16803988.1
申请日：2016-05-19
申请人： INTEL Corporation
发明人： VERGIS, George , BAINS, Kuljit S. , MCCALL, James A. , NACHIMUTHU, Murugasamy K. , KUMAR, Mohan J.
CPC分类号： G06F12/02 , G11C5/04 , G11C11/40615 , G11C11/4074 , G11C2211/4067
摘要： A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.
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公开(公告)号：EP2586028B1
公开(公告)日：2018-01-03
申请号：EP11804090.6
申请日：2011-06-27
申请人： Intel Corporation
发明人： MCCALL, James A. , BAINS, Kuljit S.
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/4093
CPC分类号： G11C7/1045 , G06F13/4086 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
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7.发明公开METHOD, APPARATUS AND SYSTEM FOR EXCHANGING COMMUNICATIONS VIA A COMMAND/ADDRESS BUS 有权方法，装置及系统中的通信从命令/地址总线
公开(公告)号：EP2936326A1
公开(公告)日：2015-10-28
申请号：EP13865408.2
申请日：2013-06-12
申请人： Intel Corporation
发明人： BAINS, Kuljit S. , MCCALL, James A.
CPC分类号： G06F12/00 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093
摘要： Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.
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公开(公告)号：EP3533058A1
公开(公告)日：2019-09-04
申请号：EP17864379.7
申请日：2017-10-30
申请人： Intel Corporation
发明人： COX, Christopher E. , BAINS, Kuljit , MOZAK, Christopher P. , MCCALL, James A. , VASANTH, Akshith , NALE, Bill
IPC分类号： G11C11/4096 , G11C11/4074 , G11C7/10
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9.发明公开
公开(公告)号：EP3503697A1
公开(公告)日：2019-06-26
申请号：EP18207421.1
申请日：2018-11-20
申请人： INTEL Corporation
发明人： DU, Daqiao , ZHOU, Zhen , LIAO, Jun , MCCALL, James A. , LI, Xiang , XIAO, Kai , ZHANG, Zhichao
摘要： A system for a three-dimensional ("3D") printed circuit board ("PCB") (102) to printed circuit board (104) interface is provided. A first PCB (102) includes first landing pads (122) disposed on one or more edges (114) of the first PCB (102). The first landing pads (122) electrically couple to conductive pins (132) or second landing pads (144) disposed on a second PCB (104). The second landing pads (144) may be disposed in a slot (142) in the second PCB (104). The interface between the first landing pads (122) and the second landing pads (144) may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.
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公开(公告)号：EP2936326B1
公开(公告)日：2018-09-05
申请号：EP13865408.2
申请日：2013-06-12
申请人： Intel Corporation
发明人： BAINS, Kuljit S. , MCCALL, James A.
IPC分类号： G11C7/10 , G06F13/42 , G06F13/14 , G06F13/16 , G11C7/22 , G11C11/4076 , G11C11/4093 , G06F12/00 , G11C11/4072
CPC分类号： G06F12/00 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/4093
摘要： Techniques and mechanisms for exchanging information from a memory controller to a memory device via a command/address bus. In an embodiment, the memory device samples a first portion of a command during a first sample period and samples a second portion of the command during a second sample period, the first portion and second portion exchanged via the command/address bus. The first sample period and the second sample period are concurrent with, respectively, a first transition of a clock signal and a second transition of the clock signal. In another embodiment, a mode of the memory device determines a relationship between the first transition and the second transition.
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