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    A system and method for testing and configuring semiconductor functional circuits
    51.
    发明公开
    A system and method for testing and configuring semiconductor functional circuits 审中-公开
    系统和方法进行测试和配置半导体函数电路

    公开(公告)号：EP2163910A3

    公开(公告)日：2010-09-15

    申请号：EP09178413.2

    申请日：2004-09-13

    申请人： Nvidia Corporation

    发明人： Diamond, Michael B. ,  Montrym, John S. ,  Van Dyke, James M. ,  Nagy, Michael B. ,  Treichler, Sean J.

    IPC分类号： G06F11/00 ,  H01L21/66 ,  G01R31/3185

    CPC分类号： G01R31/318544 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318566 ,  G06F11/22 ,  G06F11/2289 ,  G06F11/267

    摘要： Disclosed here are systems and methods to enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors including manufacturing defects, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly). Functional component operational behavior is tested and analyzed at various levels of configuration abstraction and component organization (e.g., topological inversion analysis). The testing and analysis can be performed in parallel on numerous functional components. Functional component configuration related information is presented in a graphical user interface (GUI) at various levels of granularity and in real time.; The graphical user interface can facilitate user interaction in recognizing failure patterns, production test tuning and field configuration algorithm adjustment. The testing and analysis information can also be organized in a variety of convenient database formats.

    METHOD AND APPARATUS FOR PROVIDING A DECOUPLED POWER MANAGEMENT STATE
    54.
    发明授权
    METHOD AND APPARATUS FOR PROVIDING A DECOUPLED POWER MANAGEMENT STATE 有权
    方法和设备提供性能解耦经营状况

    公开(公告)号：EP1508081B1

    公开(公告)日：2009-07-22

    申请号：EP03729134.1

    申请日：2003-05-23

    申请人： NVIDIA Corporation

    发明人： HICOK, Gary, D

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203

    摘要： A novel method and apparatus for providing a decoupled power management state. The present invention decouples the operating system's perspective of the power management state from that of the actual hardware state of a host resource. Namely, the resources (230) of a host computer (100) can still operate and provide functionality while the host operating system (220) is "off", while still providing power saving to the host system and user.

    ADAPTIVE LOAD BALANCING IN A MULTI-PROCESSOR GRAPHICS PROCESSING SYSTEM
    56.
    发明授权
    ADAPTIVE LOAD BALANCING IN A MULTI-PROCESSOR GRAPHICS PROCESSING SYSTEM 有权
    自适应负载均衡在多处理器图形处理系统

    公开(公告)号：EP1661092B1

    公开(公告)日：2009-01-14

    申请号：EP04781366.2

    申请日：2004-08-17

    申请人： NVIDIA Corporation

    发明人： DIARD, Franck, R.

    IPC分类号： G06T15/00 ,  G06F9/46

    CPC分类号： G06T15/005 ,  G06T2210/52 ,  G09G5/393 ,  G09G2352/00

    摘要： Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback data indicating completion of the rendering. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the display area is re-partitioned to increase a size of the portion assigned to the less heavily loaded processor and to decrease a size of the portion assigned to the more heavily loaded processor.

    MULTIPLE NETWORK PROTOCOL ENCODER/DECODER AND DATA PROCESSOR
    57.
    发明授权
    MULTIPLE NETWORK PROTOCOL ENCODER/DECODER AND DATA PROCESSOR 失效
    ENKODER / DEKODER MEHRERER NETZWERKPROTOKOLLE UND DATENPROZESSOR

    公开(公告)号：EP0935855B1

    公开(公告)日：2008-12-10

    申请号：EP97944464.3

    申请日：1997-09-26

    申请人： NVIDIA Corporation

    发明人： MINAMI, John, Shigeto ,  KOYAMA, Ryo ,  JOHNSON, Michael, Ward ,  SHINOHARA, Masaru ,  POFF, Thomas, C. ,  BURKES, Daniel, F.

    IPC分类号： H04J3/16 ,  H04J3/22

    CPC分类号： H04L69/12 ,  H04L47/50 ,  H04L47/6225 ,  H04L47/623 ,  H04L49/90 ,  H04L49/901 ,  H04L69/16 ,  H04L69/161 ,  H04L69/32

    摘要： A multiple network protocol encoder/decoder comprising a network protocol layer (101), data handler (102), O.S. State machine (104), and memory manager (103) state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine (101) which decodes network protocols such as TCP, IP, user Data Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler (102) which consists of data state machines (104) that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML). Each data state machine (104) reacts accordingly to the pertinent data, and any data that are required by more than one data state machine (104) is provided to each state machine concurrently, and any data required more than once by a specific data state machine, are placed in a specific memory location (206) with a pointer designating such data; thereby ensuring minimal memory usage. Resulting display data are immediately passed to a display controller (205). Any outgoing network packets are created by the data state machines and passed through the network protocol state machine which adds header information and forwards the resulting network packet via a transport level mechanism.

    摘要翻译： 一种多网络协议编码器/解码器，包括网络协议层，数据处理器，O.S. 状态机和内存管理器状态机在硬件门级实现。 网络协议层状态机通过网络协议层状态机从物理传输层次机制接收网络数据包，每个接收到一个字节同时解码TCP，IP，用户数据报协议（UDP），PPP和Raw Socket等网络协议。 每个协议处理程序从数据包中分析和剥离标题信息，不需要中间存储器。 生成的数据被传递给数据处理程序，数据处理程序由解码数据格式（如电子邮件，图形，超文本传输​​协议（HTTP），Java和超文本标记语言（HTML））的数据状态机组成。 每个数据状态机相应地对相关数据做出反应，同时向每个状态机提供多个数据状态机所需的任何数据，并且由特定数据状态机多次需要的任何数据被放置在 具有指定这种数据的指针（从而确保最小的存储器使用）的指针存储器位置。 产生的显示数据立即传递到显示控制器。 任何传出的网络数据包都是由数据状态机创建的，并通过网络协议状态机进行传输，该状态机添加标题信息，并通过传输级别机制转发生成的网络数据包。

    Defective pixel management for flat panel displays
    58.
    发明公开
    Defective pixel management for flat panel displays 审中-公开
    用于平板显示器像素缺陷管理

    公开(公告)号：EP1746493A3

    公开(公告)日：2008-09-24

    申请号：EP06015309.5

    申请日：2006-07-21

    申请人： Nvidia Corporation

    发明人： Liu, Li

    IPC分类号： G06F3/147 ,  G09G3/20

    CPC分类号： G09G3/20 ,  G09G3/2003 ,  G09G5/02 ,  G09G2330/10

    摘要： Systems and methods for identifying defective pixels and adjusting an input to control display of the defective pixels may improve the quality of the image viewed on a flat panel display including one or more defective pixels. The screen position of each defective pixel is identified and stored. Adjustment information is also stored for each defective pixel. The adjustment information is used to modify a stored color value for each defective pixel or to disable one or more color components of each defective pixel prior to displaying an image on a flat panel display device including the defective pixels.

    Operating system supplemental disk caching system and method
    59.
    发明公开
    Operating system supplemental disk caching system and method 审中-公开
    额外的磁盘分期系统和方法，用于操作系统

    公开(公告)号：EP1739560A3

    公开(公告)日：2008-04-09

    申请号：EP06012909.5

    申请日：2006-06-22

    申请人： Nvidia Corporation

    发明人： Aguaviva, Raul

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0866 ,  G06F2212/313 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39

    摘要： A computer system utilizes subsystem supplemental memory resources to implement operating system supplemental disk caching. A main system processor (e.g., a central processing unit) processes information associated with main system functions. A bulk memory (e.g., a hard disk) stores the information. A main system memory (e.g., a main RAM) caches portions of the bulk information. A subsystem supplemental memory (e.g., a graphics subsystem RAM) provides storage capacity for subsystem operations (e.g., graphics operations) and supplemental storage for portions of said bulk information associated with main system functions (e.g., functions performed by the main system processor). Information (e.g., main system information) cached in the subsystem supplemental memory can be accessed by the main system processor directly.