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    CACHING SENSING DEVICE DATA IN DATA STORAGE DEVICE
    1.
    发明公开
    CACHING SENSING DEVICE DATA IN DATA STORAGE DEVICE 审中-公开

    公开(公告)号：EP3338195A1

    公开(公告)日：2018-06-27

    申请号：EP16876714.3

    申请日：2016-12-15

    申请人： Western Digital Technologies, Inc.

    发明人： HORN, Robert L.

    IPC分类号： G06F13/16 ,  G06F12/0802

    CPC分类号： G06F12/0873 ,  G06F3/06 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/313

    摘要： Data is received from a sensing device of a plurality of sensing devices in communication with a device for storage in at least one memory of the device. A first cache memory or a second cache memory of the device is selected for caching the received data based at least in part on the sensing device sending the data. According to another aspect, data is received from a sensing device for storage in at least one memory of a device. It is determined whether to cache the received data based on at least one of the sensing device sending the data and information related to the received data. A cache memory is selected from among a plurality of cache memories of the device for caching the received data based at least in part on the sensing device sending the data.

    DATA STORAGE DEVICE
    2.
    发明公开
    DATA STORAGE DEVICE 审中-公开

    公开(公告)号：EP3113027A4

    公开(公告)日：2017-11-01

    申请号：EP14883990

    申请日：2014-02-27

    申请人： MITSUBISHI ELECTRIC CORP

    发明人： TSUJIO RYOTA ,  KATO TETSURO ,  IDO YASUNORI

    IPC分类号： G06F12/08 ,  G06F12/0866

    CPC分类号： G06F3/0631 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/142 ,  G06F12/0866 ,  G06F2212/261 ,  G06F2212/285 ,  G06F2212/313 ,  H04L45/742

    摘要： A memory system (100) includes a plurality of volatile memory modules (11) to temporarily store data in a distributed manner, a V storing place management unit (13) included in each of the volatile memory modules (11), a plurality of nonvolatile memory modules (12) to store the data stored in each of the volatile memory modules (11) in a distributed manner, and a NV storing place management unit (14) included in each of the nonvolatile memory modules (12). Each V storing place management unit (13) and each NV storing place management unit (14) communicate and determine the destination nonvolatile memory module (12) for each volatile memory module (11). The data is transmitted to the determined destination nonvolatile memory module (12) and stored in the destination nonvolatile memory module (12).

    CACHE-AWARE BACKGROUND STORAGE PROCESSES
    3.
    发明公开
    CACHE-AWARE BACKGROUND STORAGE PROCESSES 审中-公开
    CACHE-BEWUSSTES HINTERGRUNDSPEICHERUNGSVERFAHREN

    公开(公告)号：EP3133496A1

    公开(公告)日：2017-02-22

    申请号：EP16178276.8

    申请日：2016-07-06

    申请人： Strato Scale Ltd.

    发明人： Traeger, Avishay

    IPC分类号： G06F12/0866 ,  G06F3/06

    CPC分类号： G06F12/0804 ,  G06F12/0238 ,  G06F12/0866 ,  G06F12/0868 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/281 ,  G06F2212/313 ,  G06F2212/7205 ,  G06F2212/7207

    摘要： A system (20) for data storage includes one or more storage devices (36, 52), a cache memory (40, 60), and one or more processors (32, 50). The processors are configured to store data in the storage devices, to cache part of the stored data in the cache memory, and to apply a background maintenance process to at least some of the data stored in the storage devices, including modifying the background maintenance process depending on the part of the data that is cached in the cache memory.

    摘要翻译： 一种用于数据存储的系统（20）包括一个或多个存储设备（36,52），高速缓冲存储器（40,60）和一个或多个处理器（32,50）。 处理器被配置为将数据存储在存储设备中，以将存储的数据的一部分缓存在高速缓冲存储器中，并且对存储在存储设备中的至少一些数据应用后台维护过程，包括修改后台维护过程 这取决于缓存在缓存中的部分数据。

    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME
    4.
    发明公开
    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME 审中-公开
    HYBRIDSPEICHERMODUL UND -SYSTEM UND VERFAHREN ZUM BETRIEB DAVON

    公开(公告)号：EP3066570A2

    公开(公告)日：2016-09-14

    申请号：EP14860330.1

    申请日：2014-11-07

    申请人： Netlist, Inc.

    发明人： LEE, Hyun ,  BHAKTA, Jayesh, R. ,  CHEN, Chi, She ,  SOLOMON, Jeffery, C. ,  MARTINEZ, Mario, Jesus ,  LE, Hao ,  CHOI, Soon, J.

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F11/1004 ,  G06F11/108 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313

    摘要： A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non- volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non- volatile memory subsystem, and the C/A bus. The module controller is configured to control intra- module data transfers between the volatile memory subsystem and the non- volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    摘要翻译： 存储器模块包括被配置为耦合到计算机系统中的存储器通道并且能够用作计算机系统的主存储器的非易失性存储器子系统，为计算机系统提供存储的非易失性存储器子系统以及耦合到该存储器系统的模块控制器 易失性存储器子系统，非易失性存储器子系统和C / A总线。 模块控制器被配置为控制易失性存储器子系统和非易失性存储器子系统之间的模块内数据传输。 模块控制器还被配置为监视C / A总线上的C / A信号，并根据C / A信号调度模块内数据传输，使得模块内数据传输不与对易失性的访问冲突 内存子系统由内存控制器。

    Computer system, and arrangement of data control method
    6.
    发明公开
    Computer system, and arrangement of data control method 有权
    电脑系统和电脑系统（Datensteuerungsverfahren）

    公开(公告)号：EP2869203A1

    公开(公告)日：2015-05-06

    申请号：EP14190870.7

    申请日：2014-10-29

    申请人： Hitachi, Ltd.

    发明人： Kondo, Nobukazu ,  Sugimoto, Ken ,  Fukumura, Yuusuke

    IPC分类号： G06F12/08

    CPC分类号： H04L67/2842 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F15/167 ,  G06F2212/1041 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/262 ,  G06F2212/263 ,  G06F2212/311 ,  G06F2212/313

    摘要： A computer system include a service server (200), a storage server (300) and a management server (100), wherein the service server (200) includes a operating system (210), wherein the operating system (210) includes a cache driver (213), wherein the storage server (300) manages a plurality of tiered storage areas each having an access performance different from one another, wherein the management server (100) includes an alert setting information generation part (122) for generating alert setting information for the service servers to transmit alert information notifying a trigger to change an arrangement of data in accordance with a state of the service, and a control information generation part (121) for generating cache control information including a first command for controlling an arrangement of cache data on a storage cache and tier control information including a second command for controlling an arrangement of the data on the plurality of tiered storage areas.

    摘要翻译： 计算机系统包括服务服务器（200），存储服务器（300）和管理服务器（100），其中所述服务服务器（200）包括操作系统（210），其中所述操作系统（210）包括高速缓存 驱动器（213），其中所述存储服务器（300）管理各自具有彼此不同的访问性能的多个分层存储区域，其中所述管理服务器（100）包括用于生成警报设置的警报设置信息生成部分（122） 用于服务服务器发送根据服务状态通知触发改变数据排列的警报信息的信息;以及用于产生高速缓存控制信息的控制信息生成部分，所述控制信息生成部分包括用于控制 在存储高速缓存上的缓存数据和包括用于控制多个分层存储区域上的数据的排列的第二命令的层控制信息。

    Operating system supplemental disk caching system and method
    8.
    发明公开
    Operating system supplemental disk caching system and method 审中-公开
    额外的磁盘分期系统和方法，用于操作系统

    公开(公告)号：EP1739560A3

    公开(公告)日：2008-04-09

    申请号：EP06012909.5

    申请日：2006-06-22

    申请人： Nvidia Corporation

    发明人： Aguaviva, Raul

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0866 ,  G06F2212/313 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39

    摘要： A computer system utilizes subsystem supplemental memory resources to implement operating system supplemental disk caching. A main system processor (e.g., a central processing unit) processes information associated with main system functions. A bulk memory (e.g., a hard disk) stores the information. A main system memory (e.g., a main RAM) caches portions of the bulk information. A subsystem supplemental memory (e.g., a graphics subsystem RAM) provides storage capacity for subsystem operations (e.g., graphics operations) and supplemental storage for portions of said bulk information associated with main system functions (e.g., functions performed by the main system processor). Information (e.g., main system information) cached in the subsystem supplemental memory can be accessed by the main system processor directly.

    MEMORY ACCESS METHOD, APPARATUS AND SYSTEM
    9.
    发明公开
    MEMORY ACCESS METHOD, APPARATUS AND SYSTEM 审中-公开

    公开(公告)号：EP3321809A4

    公开(公告)日：2018-07-25

    申请号：EP15901909

    申请日：2015-08-21

    申请人： HUAWEI TECH CO LTD

    发明人： LUO DAXIN ,  LI GANG ,  PAN SHUNCHENG

    IPC分类号： G06F12/00 ,  G06F12/0871

    CPC分类号： G06F12/0893 ,  G06F12/00 ,  G06F12/0871 ,  G06F2212/1008 ,  G06F2212/154 ,  G06F2212/163 ,  G06F2212/313 ,  G06F2212/608

    摘要： A memory access method, apparatus, and system are disclosed, and relate to the field of computer technologies, to appropriately use storage space of a local memory device, so as to improve overall performance of a system. The method is applied to a system that includes the local memory device and a remote memory device. The method includes: receiving a memory access request that carries address information of a to-be-accessed memory area (S301); determining the to-be-accessed memory area indicated by the address information (S302); when the to-be-accessed memory area is in a local memory, performing an access operation on the to-be-accessed memory area according to the memory access request, where the local memory device includes the local memory and a remote cache; and when the to-be-accessed memory area is in the remote memory device, and the remote cache includes a cache block corresponding to the to-be-accessed memory area, performing an access operation on the cache block according to the memory access request (S303).