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62 条记录 (耗时 0.017 秒)

    Semiconductor memory device having reduced parasitic capacities between bit lines
    54.
    发明公开
    Semiconductor memory device having reduced parasitic capacities between bit lines 失效
    与位线之间的降低的寄生电容的半导体存储器件。

    公开(公告)号：EP0457591A2

    公开(公告)日：1991-11-21

    申请号：EP91304409.5

    申请日：1991-05-16

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： G11C7/00 ,  G11C11/409

    CPC分类号： G11C7/18 ,  G11C11/4097

    摘要： In a semiconductor memory device having a memory cell array (MCA) and sense amplifiers (SA₁, SA₂, ...) connected by bit lines (BL₁, BL ₂, ...), a conductive shield plate (SLD) is arranged over the bit lines and between memory cell array and the sense amplifiers.

    摘要翻译： 在具有存储器单元阵列（MCA）的半导体存储装置和感测由位线（BL1，BL2，...），导电屏蔽板（SLD），其连接放大器（SA1，SA2，...）被布置在 存储单元阵列和读出放大器之间的位线和。

    Semiconductor device having a superconductive wiring
    55.
    发明公开
    Semiconductor device having a superconductive wiring 失效
    具有超导线的半导体器件

    公开(公告)号：EP0295708A3

    公开(公告)日：1989-09-06

    申请号：EP88109700.0

    申请日：1988-06-16

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L23/52 ,  H01L21/90 ,  H01L39/24

    CPC分类号： H01L23/53285 ,  H01L23/532 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On a IC where the wiring layer (21) is formed of supercon­ductive material, an electrode (23) formed of normal metals, i. e. non-superconductive metals, such as aluminum, connects a part of semiconductor region (4) via a barrier metal, such as TiN, to the superconductive layer (21) wiring at least at the superconductive layer (21) wiring's side wall which is essentially orthogonal to the layer wiring. Accordingly, even when the wiring layer (21) is anisotro­pically superconductive mainly in direction parallel to the plane of the deposition, the superconductive property is fully enjoyed while the copper atoms in the supercon­ductive material and the silicon atoms in the semiconductor region (4) of the IC do not produce undesirable alloy, resulting in improved reliability of the IC operation, i. e. the semiconductor material as well as the supercon­ductive material is not deteriorated.

    Multiple-value logic circuitry
    56.
    发明公开
    Multiple-value logic circuitry 失效
    多值逻辑电路

    公开(公告)号：EP0220020A3

    公开(公告)日：1988-09-07

    申请号：EP86307758

    申请日：1986-10-08

    申请人： FUJITSU LIMITED

    发明人： Yokoyama, Naoki ,  Taguchi, Masao

    IPC分类号： G11C11/56 ,  H03K03/29 ,  H03K03/36

    CPC分类号： B82Y10/00 ,  F16L55/00 ,  G11C11/39 ,  G11C11/56 ,  G11C2211/5614 ,  H03K3/29 ,  H03K3/36

    摘要： Logic circuitry (1) includes a resonant-tunneling transistor ( 1) and a resistor (13) connected in series thereto. The resonant-tunneling transistor has a superlattice structure and may be a resonant-tunneling hot electron transistor or a resonant-tunneling bipolar transistor. The resonant-tunneling transistor is operable to flow a current, between a collector and an emitter, having one of at least three different current values of a first, a second or a third value in response to a base voltage (V IN ) in one of three different voltage values of a first, second or a third value. The third current value lies between the first and second current values, and the second voltage value lies between the first and third voltage values. The logic circuitry outputs one of at least three states having a high value, a low value, and a value approximately in between the high and low values in response to a signal applied to the logic circuitry the signal having an amplitude of one of the first to third voltage values.

    Semiconductor device
    58.
    发明公开
    Semiconductor device 失效
    半导体器件

    公开(公告)号：EP0055558A3

    公开(公告)日：1983-10-05

    申请号：EP81305941

    申请日：1981-12-18

    申请人： FUJITSU LIMITED

    发明人： Toyokura, Nobuo ,  Taguchi, Masao

    IPC分类号： H01L21/225 ,  H01L29/94 ,  H01L27/10 ,  H01L21/314 ,  G11C11/24

    CPC分类号： H01L21/28185 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/28229 ,  H01L21/31683 ,  H01L21/3185 ,  H01L27/04 ,  H01L27/10805 ,  H01L27/1085 ,  H01L29/517 ,  H01L29/94

    摘要： An insulating film (23) of a higher dielectric constant than silicon dioxide, for example of tantalum oxide, is formed on a p-type substrate (21). The insulating film (23) contains an n-type impurity, for example phosphorus. An electrode (24), for example of molybdenum silicide, is formed on the insulating film (23). By a heat treatment carried out for example for 30 minutes at a temperature of 1000°C an n-type region (25) is formed in the p-type substrate (21) by diffusion of impurity (phosphorus) from the insulating film (23), into the surface of the substrate (21). Thereby an MIS type capacitor can be provided in which the insulating film (23) has a higher dielectric constant than silicon dioxide, whereby an increased amount of electric charge can be held in a capacitor of the same size as one in which an insulating film is provided of silicon dioxide. By the provision of the n-type inversion region (25) the capacitor can be charged up to the voltage of the power source connected to the electrode (24). By the diffusion of impurities from the insulating film (23) into the substrate (21) to form the region (25), the region (25) is formed in an accurate self-aligning fashion.

    摘要翻译： 在p型衬底（21）上形成介电常数高于二氧化硅（例如氧化钽）的绝缘膜（23）。 绝缘膜（23）含有n型杂质，例如磷。 在绝缘膜（23）上形成例如硅化钼的电极（24）。 通过例如在1000℃的温度下进行30分钟的热处理，通过来自绝缘膜（23）的杂质（磷）的扩散在p型衬底（21）中形成n型区域（25） ）到衬底（21）的表面中。 由此，可以提供绝缘膜（23）的介电常数比二氧化硅高的MIS型电容器，由此可以在与绝缘膜为相同尺寸的电容器中保持增加量的电荷 提供二氧化硅。 通过提供n型反转区域（25），电容器可被充电到与电极（24）连接的电源的电压。 通过杂质从绝缘膜（23）扩散到衬底（21）中以形成区域（25），区域（25）以精确的自对准方式形成。

    Semiconductor memory device
    59.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0061859A2

    公开(公告)日：1982-10-06

    申请号：EP82301308.1

    申请日：1982-03-15

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L27/10

    CPC分类号： H01L29/42368 ,  H01L27/10805

    摘要： A semiconductor memory device having memory cells each of which stores data in the form of the width of a depletion layer, and each of which comprises a semiconductor substrate having one type of conductivity; a region having an opposite type of conductivity formed on the surface portion of the semiconductor substrate; a depletion-type channel region of the one type of conductivity formed on the region having the opposite type of conductivity; a gate insulator which is formed on the surface of the channel region; and a gate electrode formed on the gate insulator; a portion of the gate insulator having a reduced thickness, and a portion of the channel region under the thin portion of the gate insulator being surrounded by the region having the opposite type of conductivity and by the remaining portions of the channel region in the semiconductor substrate.

    摘要翻译： 一种具有存储单元的半导体存储器件，每个存储单元以耗尽层的宽度的形式存储数据，并且每个存储单元包括具有一种导电类型的半导体衬底; 在半导体衬底的表面部分上形成具有相反类型导电性的区域; 在具有相反导电类型的区域上形成的一种导电类型的耗尽型沟道区; 在沟道区域的表面上形成的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极; 所述栅极绝缘体的一部分具有减小的厚度，并且所述栅极绝缘体的所述薄部分下方的所述沟道区域的一部分被所述具有相反导电类型的区域和所述半导体衬底中的所述沟道区域的其余部分 。

    Method of manufacturing a semiconductor device
    60.
    发明公开
    Method of manufacturing a semiconductor device 失效
    Verfahren zur Herstellung einer Halbleiteranordnung。

    公开(公告)号：EP0055558A2

    公开(公告)日：1982-07-07

    申请号：EP81305941.7

    申请日：1981-12-18

    申请人： FUJITSU LIMITED

    发明人： Toyokura, Nobuo ,  Taguchi, Masao

    IPC分类号： H01L21/225 ,  H01L29/94 ,  H01L27/10 ,  H01L21/314

    CPC分类号： H01L21/28185 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/28229 ,  H01L21/31683 ,  H01L21/3185 ,  H01L27/04 ,  H01L27/10805 ,  H01L27/1085 ,  H01L29/517 ,  H01L29/94

    摘要： An insulating film (23) of a higher dielectric constant than silicon dioxide, for example of tantalum oxide, is formed on a p-type substrate (21). The insulating film (23) contains an n-type impurity, for example phosphorus. An electrode (24), for example of molybdenum silicide, is formed on the insulating film (23). By a heat treatment carried out for example for 30 minutes at a temperature of 1000°C an n-type region (25) is formed in the p-type substrate (21) by diffusion of impurity (phosphorus) from the insulating film (23), into the surface of the substrate (21).
    Thereby an MIS type capacitor can be provided in which the insulating film (23) has a higher dielectric constant than silicon dioxide, whereby an increased amount of electric charge can be held in a capacitor of the same size as one in which an insulating film is provided of silicon dioxide. By the provision of the n-type inversion region (25) the capacitor can be charged up to the voltage of the power source connected to the electrode (24). By the diffusion of impurities from the insulating film (23) into the substrate (21) to form the region (25), the region (25) is formed in an accurate self-aligning fashion.

    摘要翻译： 在p型基板（21）上形成具有比二氧化硅更高介电常数（例如氧化钽）的绝缘膜（23）。 绝缘膜（23）含有n型杂质，例如磷。 在绝缘膜（23）上形成例如硅化钼的电极（24）。 通过在1000℃的温度下进行例如30分钟的热处理，通过从绝缘膜（23）扩散杂质（磷），在p型基板（21）中形成n型区域（25） ）到基板（21）的表面中。 因此，可以提供其中绝缘膜（23）具有比二氧化硅更高的介电常数的MIS型电容器，由此可以将增加的电荷量保持在与一个相同尺寸的电容器中 绝缘膜由二氧化硅提供。 通过设置n型反转区域（25），可以将电容器充电至连接到电极（24）的电源的电压。 通过将杂质从绝缘膜（23）扩散到基板（21）中以形成区域（25），区域（25）以精确的自对准方式形成。