公开(公告)号：EP2586127A4

公开(公告)日：2014-02-12

申请号：EP11807201

申请日：2011-05-09

申请人： FREESCALE SEMICONDUCTOR INC

发明人： STOCKINGER MICHAEL A ,  CAMARENA JOSE A ,  ZHANG WENZHONG

IPC分类号： H03K17/16 ,  H03K17/10 ,  H03K19/003

CPC分类号： H03K17/102

公开(公告)号：EP2691854A1

公开(公告)日：2014-02-05

申请号：EP11862267.9

申请日：2011-03-30

申请人： Freescale Semiconductor, Inc.

发明人： VASKEVICH, Lev ,  ELNEKAVE, Mark ,  PELED, Yuval ,  ROZENBERG, Idan

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3853

摘要： There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if any one or more of the following is asserted: the number of VLES groups available for dispatch is less than a predetermined starvation threshold, OR the number of VLES groups available for dispatch is indicative of going below a predetermined upper limit threshold, OR the number of VLES groups available for dispatch is indicative of being between the predetermined starvation threshold and the predetermined upper limit threshold, and a fetch-ahead of a Fetch Set occurred in an immediately previous cycle.

公开(公告)号：EP2680307A2

公开(公告)日：2014-01-01

申请号：EP13173268.7

申请日：2013-06-21

申请人： Freescale Semiconductor, Inc.

发明人： Daniels, Dwight L. ,  Hooper, Stephen R. ,  Magnus, Alan J. ,  Poarch, Justin E.

IPC分类号： H01L23/495 ,  H01L21/56

摘要： A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.

摘要翻译： 一种用于提高组装在引线框架（112）中的集成电路封装（140）的锯切质量和润湿性的结构和方法，所述引线框架在引线中具有半蚀刻凹槽（134）。 形成半导体器件封装的方法包括提供具有多个引线框架的引线框条（110）。 引导框架中的每一个包括在分割条带之前至少部分地填充有材料（400）的凹陷（130）。

公开(公告)号：EP2680299A2

公开(公告)日：2014-01-01

申请号：EP13172894.1

申请日：2013-06-19

申请人： Freescale Semiconductor, Inc.

发明人： Bode, Hubert ,  Chen, Weize ,  De Souza, Richard J. ,  Parris, Patrice M

IPC分类号： H01L21/336 ,  H01L29/78

摘要： Embodiments of semiconductor devices (200, 800) and driver circuits (110) include a semiconductor substrate (210, 810) having a first conductivity type, an isolation structure (including a sinker region (222, 822) and a buried layer (220, 820)), an active device within a portion (230, 830) of the substrate contained by the isolation structure, and a resistor circuit (160). The buried layer (220, 820) is positioned below the top substrate surface (212, 812), and has a second conductivity type. The sinker region (222, 822) extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a current carrying region (236, 238, 836, 838) (e.g., a source region of the first conductivity type and/or a drain region of the second conductivity type), and the resistor circuit (160) is connected between the isolation structure and the current carrying region. The resistor circuit may include one or more resistor networks (446, 546, 646, 746, 1046, 1146, 1246, 1346) and, optionally, a Schottky diode (410, 510, 1010, 1110) and/or one or more PN diode(s) (610, 710, 1210, 1310) in series and/or parallel with the resistor network(s).

摘要翻译： 半导体器件（200，800）和驱动器电路（110）的实施例包括具有第一导电类型，（对隔离结构，包括下沉区域（222，822）和一个埋层（220的半导体衬底（210，810）， 820）），（上由隔离结构包含在衬底的一部分（230，830）内的有源器件，以及电阻器电路160）。 掩埋层（220，820）定位在所述顶表面的衬底（212，812）的下方，并具有第二导电类型。 下沉区域（222，822）的顶部表面与所述掩埋层基板之间延伸，并且具有第二导电类型。 有源器件包括：（236，238，836，838）（例如，第一导电类型和/或第二导电类型的漏极区域的源极区域），和上述电阻电路（160）连接的载流区域 隔离结构和载流区之间。 电阻器电路可以包括一个或多个电阻网络（446，546，646，746，1046，1146，1246，1346）和，任选地，肖特基二极管（410，510，1010，1110）和/或一个或多个PN 二极管（一个或多个）（610，710，1210，1310）在串联和/或平行于所述电阻网络（一个或多个）。

公开(公告)号：EP2676369A1

公开(公告)日：2013-12-25

申请号：EP11754552.5

申请日：2011-02-18

申请人： Freescale Semiconductor, Inc.

发明人： SYNGAEVSKIY, Vasily Alekseyevich ,  GUILLOT, Laurent ,  ROSADO, Philippe ,  SHUVALOV, Denis Sergeevich ,  SOLDATOV, Alexander Petrovich

IPC分类号： H03K17/082

CPC分类号： H02H3/093 ,  H03K17/082

摘要： An overcurrent protection device comprises a maximum-allowed-current unit and a power switch. The maximum-allowed-current unit determines a maximum allowed current in real-time. The maximum allowed current is determined at least partially on an instantaneous level of a load voltage. The load voltage is a voltage across a load to be powered. The power switch is connectable with a switch input to a voltage supply and with a switch output to the load, for providing power to said load. The power switch has a conductive state and a nonconductive state, and is arranged to assume the nonconductive state in response to an indication that a current through the power switch is exceeding the maximum allowed current. A method of operating a power switch is also described.

摘要翻译： 过电流保护装置包括最大允许电流单元和电源开关。 最大允许电流单位实时确定最大允许电流。 最大允许电流至少部分地在负载电压的瞬时电平上确定。 负载电压是要通电的负载两端的电压。 电源开关可连接到电源的开关输入和开关输出到负载，以向所述负载提供电力。 功率开关具有导通状态和非导通状态，并且被布置为响应于通过功率开关的电流超过最大允许电流的指示而呈现非导通状态。 还描述了操作电源开关的方法。

公开(公告)号：EP2263254A4

公开(公告)日：2013-12-25

申请号：EP09727967

申请日：2009-02-05

申请人： FREESCALE SEMICONDUCTOR INC

发明人： YANG HONGNING ,  ZUO JIANG-KAI

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/0705 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.

公开(公告)号：EP2672486A2

公开(公告)日：2013-12-11

申请号：EP13169553.8

申请日：2013-05-28

申请人： Freescale Semiconductor, Inc.

发明人： Ramamurthy, Hema ,  Ramaraju, Ravindraraj

IPC分类号： G11C8/08 ,  G11C8/18 ,  G11C7/22

CPC分类号： G11C8/10 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18

摘要： A memory (10) includes a plurality of latching predecoders (20, 22, 24, 26), each including a first transistor (30, 136) coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor (32, 108) coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor (34, 110) coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor (36, 112) coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor (38, 114) coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value (A6A7b) during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

摘要翻译： 存储器（10）包括多个锁存预解码器（20,22,24,26），每个锁存预解码器包括耦合在电源电压和锁存器之间并具有耦合到时钟信号的控制电极的第一晶体管（30,136） ; 耦合到所述第一晶体管并且具有耦合到第一地址位信号的控制电极的第二晶体管（32,108） 耦合到所述第二晶体管并且具有耦合到第二地址位信号的控制电极的第三晶体管（34,110） 第四晶体管（36,112），其耦合到所述第三晶体管并具有耦合到所述时钟信号的延迟和反相形式的控制电极; 第五晶体管（38,114），耦合在所述第四晶体管和地之间并且具有耦合到所述时钟信号的控制电极; 以及在时钟周期的第二部分期间在时钟信号的时钟周期的第一部分和预定逻辑电平期间提供预解码值（A6A7b）的输出。

公开(公告)号：EP2671227A1

公开(公告)日：2013-12-11

申请号：EP11857657.8

申请日：2011-01-31

申请人： Freescale Semiconductor, Inc.

发明人： PRIEL, Michael ,  KUZMIN, Dan ,  ROZEN, Anton

IPC分类号： G11C5/14

CPC分类号： G05F1/462 ,  G11C5/147 ,  G11C7/04 ,  G11C16/30

摘要： An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.

摘要翻译： 一种集成电路（IC）装置设置确实包括布置在第一输入，用于接收电压供应信号其在第二输入接收控制信号其在雅舞的调节接收电压供应信号的至少一个内部电压调节器 接收的控制信号，并在它们的输出端提供调节的电压供应信号。 所述IC器件包括：至少一个另外的电压调节功率控制模块可操作地耦合到所述至少一个内部电压调节器的第二输入端和布置成提供所述控制信号于此。 电压调节功率控制模块被进一步设置成接收至少一个集成电路设备条件指示，并产生用于至少部分地基于上可用的热功率预算IC装置在对应于所述至少一个内部电压调节器的控制信号 至少一个IC装置的条件指示。

公开(公告)号：EP2669807A2

公开(公告)日：2013-12-04

申请号：EP13169521.5

申请日：2013-05-28

申请人： Freescale Semiconductor, Inc.

发明人： McCarthy, Daniel M. ,  Circello, Joseph ,  Hausman, Kirsten A.

IPC分类号： G06F12/14

CPC分类号： G06F12/1491 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F12/023 ,  G06F12/1441 ,  G06F2212/1044 ,  G06F2212/1052

摘要： Embodiments include processing systems (110) that determine (308), based on an instruction address range indicator stored in a first register (132, 212), whether a next instruction fetch address corresponds to a location within a first memory region (216, 218) associated with a current privilege state or within a second memory region (216, 218) associated with a different privilege state. When the next instruction fetch address is not within the first memory region (216, 218), the next instruction is allowed to be fetched (314) only when a transition to the different privilege state is legal (310). In a further embodiment, when a data access address is generated for an instruction (316), a determination is made (320), based on a data address range indicator stored in a second register (133, 222), whether access to a memory location corresponding to the data access address is allowed. The access is allowed (318) when the current privilege state is a privilege state in which access to the memory location is allowed.

公开(公告)号：EP2482456A3

公开(公告)日：2013-11-27

申请号：EP12151642.1

申请日：2012-01-18

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Jarrar, Anis M. ,  Singhania, Anuj ,  Weston, Bryan T.

IPC分类号： H03K19/0185 ,  H03K3/356

CPC分类号： H03K19/018521 ,  H03K3/356182

摘要： A level shifter (300) including input (VDDIN) and output (VDDOUT) power nodes, input (VSSIN) and output (VSSOUT) reference nodes, input (IN) and output (OUT) signal nodes, and a lever shifter network (405,410,415,420,425,430,440). The input power and input reference nodes operate within a first power domain (202, 204, 206) and the output power and output reference nodes operate within a second power domain (202,204,206). The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power (BYP_VDD) and/or ground (BYP_VSS) bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input (ISO) to assert the output to a known level.