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    SPREAD-SPECTRUM GMSK/M-ARY RADIO WITH OSCILLATOR FREQUENCY CORRECTION
    61.
    发明公开
    SPREAD-SPECTRUM GMSK/M-ARY RADIO WITH OSCILLATOR FREQUENCY CORRECTION 审中-公开
    SPREIZSPEKTORUM-GMSK / M-ARYFUNGERÄTMIT OSZILLATOR FREQUENZKORRECTION

    公开(公告)号：EP1188249A4

    公开(公告)日：2006-12-27

    申请号：EP00932152

    申请日：2000-05-05

    申请人： NAVCOM TECH INC

    发明人： ALISOBHANI JALAL ,  LEIMER DONALD K ,  WOO RICHARD KAI-TUEN ,  KAPLAN MARK PHILIP

    IPC分类号： H03L7/091 ,  H03L7/181 ,  H04B1/707 ,  H04J13/00 ,  H04L27/00 ,  H04L27/20 ,  H04L27/22

    CPC分类号： H04J13/10 ,  H03L7/091 ,  H03L7/181 ,  H04B1/707 ,  H04J13/0029 ,  H04L27/2017 ,  H04L27/22 ,  H04L2027/0028 ,  H04L2027/0055

    摘要： A communication device includes a transmitter (21) and receiver. The transmitter (21) includes an M-ary encoder (23) configured to generate an M-1 number of distinctive symbols each comprising k bits. M is equal to 2k and k is a positive integer. The transmitter (21) also includes a code generator (25) configured to produce spread spectrum codeword sequence based on the symbols generated by the M-ary encoder and based on a first and second Gold code polynomials. The transmitter (21) sends a radio signal based on the spread spectrum codeword sequences to a receiver. The receiver includes a first shift register (81) configured to receive an input signal generated based on the received radio signal and a second shift register (83) configured to receive and circularly shift a locally generated codeword sequence that is identical to the codeword sequence used to encode the symbols.

    摘要翻译： 通信设备包括发射机（21）和接收机。 发送器（21）包括M元编码器（23），其被配置为生成每个包括k个比特的M-1个特征符号。 M等于2k，k是正整数。 发射机（21）还包括码生成器（25），其被配置为基于由M元编码器生成的码元并且基于第一和第二Gold码多项式来生成扩频码字序列。 发射机（21）基于扩频码字序列发送无线电信号给接收机。 接收器包括被配置为接收基于接收的无线电信号生成的输入信号的第一移位寄存器（81）和被配置为接收并循环移位与使用的码字序列相同的本地生成的码字序列的第二移位寄存器（83） 对符号进行编码。

    THERMAL DRIFT COMPENSATION SYSTEM
    63.
    发明公开
    THERMAL DRIFT COMPENSATION SYSTEM 失效
    SYSTEM FOR补偿温度漂移

    公开(公告)号：EP0996998A4

    公开(公告)日：2005-07-20

    申请号：EP98931699

    申请日：1998-06-26

    申请人： CREDENCE SYSTEMS CORP

    发明人： VANDERSCHOOT HENS CHRISTOPHER ,  WASSON TIMOTHY M

    IPC分类号： H03H11/26 ,  H03K5/13 ,  H03L7/099 ,  H03L7/181

    CPC分类号： H03L7/0805 ,  H03K5/13 ,  H03K5/131 ,  H03L7/0997 ,  H03L7/181

    摘要： A system for compensating for thermal drift of an output signal (OUT1) produced by a logic circuit (12) in response to an input CLOCK signal after a temperature dependent delay includes a variable delay circuit (14), an oscillator (26) and a digital phase lock controller (28). The delay circuit (14) delays the OUT1 signal to produce a compensated output signal (OUT2) with a variable delay controlled by input CONTROL data. The oscillator (26) generates an output signal (OSC_OUT) having a period also controlled by the input CONTROL data which is substantially proportional to the sum of the temperature dependent delay of the logic circuit (12) and the delay of the variable delay circuit (14). The digital phase lock controller (28) continually monitors the period of the OSC_OUT signal and adjusts the CONTROL data so that the period of the OSC_OUT signal remains substantially constant. This ensures that the delay between the CLOCK signal and OUT2 remains constant despite temperature dependent variations in the delay of the logic circuit (12).

    PHASE LOCKED LOOP
    64.
    发明公开
    PHASE LOCKED LOOP 审中-公开
    锁相环

    公开(公告)号：EP1350324A2

    公开(公告)日：2003-10-08

    申请号：EP02715596.9

    申请日：2002-01-09

    申请人： ADC Telecommunications Israel Ltd.

    发明人： KLIPPER, Joshua ,  NURKO, Moshe ,  AGAMI, Udi

    IPC分类号： H03L7/085

    CPC分类号： H03L7/181 ,  H03L7/085 ,  H04J3/0688

    摘要： A known local clock frequency is divided into at least two phases, and the rising and the falling edges of each of the divided signals are counted. The sum total edges in a given time period is compared to a stored sum of edges during an earlier time period of the same duration. Adjustment to the local clock is made if sufficient differences are detected.

    摘要翻译： 已知的本地时钟频率被分成至少两个相位，并且对每个分频信号的上升沿和下降沿进行计数。 将给定时间段内的总和边缘与相同持续时间的较早时间段期间存储的边缘总数相比较。 如果检测到足够的差异，则对本地时钟进行调整。

    Digital PLL circuit
    68.
    发明公开
    Digital PLL circuit 失效
    数字PLL-Schaltung

    公开(公告)号：EP1179822A1

    公开(公告)日：2002-02-13

    申请号：EP01124944.8

    申请日：1997-04-29

    申请人： Mitsumi Electric Co., Ltd.

    发明人： Okada, Isao. ,  Hirabuki, Tsuyoshi.

    IPC分类号： G11B20/14 ,  G11B20/10 ,  H03L7/06 ,  G11B19/28 ,  H02P5/00

    CPC分类号： H03L7/181 ,  E05Y2400/30 ,  G11B19/247 ,  G11B19/26 ,  G11B19/28 ,  G11B20/10 ,  G11B20/1025 ,  G11B20/1403 ,  G11B27/24 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  H03L7/08 ,  H03L7/085 ,  H03L2207/50

    摘要： A digital PLL circuit, characterised in that said digital PLL circuit comprises: measuring means (2042) for receiving an input signal which intermittently includes pulses of a predetermined pulse width and measuring edge spans of the input signal; and clock generating means (2046, 2048, 2062), when an edge span value obtained by said measuring means is within a predetermined range which is based on said predetermined pulse width, for generating a clock signal based on said edge span value.

    摘要翻译： 一种伺服电路，包括用于检测速度误差的速度误差检测装置（1044,1050），所述速度误差是从记录介质再现的再生时钟信号与基准时钟信号之间的频率差; 用于检测相位误差的相位误差检测装置（1078,1084,1092），所述相位误差是再现的时钟信号和参考时钟信号之间的相位差; 以及用于产生用于消除速度误差和相位误差的伺服信号的伺服信号产生装置（1052,1054,1057,1058,1060,1094,1046），其中所述相位误差检测装置包括：第一和第二分频 用于分别对再现的时钟信号和参考时钟信号进行分频的装置（1078,1048），其特征在于，分频比根据所述速度误差检测装置的速度误差增益的变化而改变; 以及用于检测分频再生时钟信号和分频基准时钟信号之间的相位误差的相位比较装置（1092）。

    Servo circuit, digital PLL circuit and optical disk device
    69.
    发明公开
    Servo circuit, digital PLL circuit and optical disk device 失效
    Servoschaltung，数字PLL-Schaltung和眼镜Plattengerät

    公开(公告)号：EP0805438A3

    公开(公告)日：1999-12-15

    申请号：EP97302912.7

    申请日：1997-04-29

    申请人： Mitsumi Electric Co., Ltd.

    发明人： Okada, Isao ,  Hirabuki, Tsuyoshi

    IPC分类号： G11B7/00 ,  H03L7/06 ,  G11B20/14

    CPC分类号： H03L7/181 ,  E05Y2400/30 ,  G11B19/247 ,  G11B19/26 ,  G11B19/28 ,  G11B20/10 ,  G11B20/1025 ,  G11B20/1403 ,  G11B27/24 ,  G11B27/3027 ,  G11B2220/218 ,  G11B2220/2545 ,  H03L7/08 ,  H03L7/085 ,  H03L2207/50

    摘要： A speed error detecting portion (M1; 44, 50) detects a speed error which is a frequency difference between a reproduced clock signal which is reproduced from a recording medium and a reference clock signal. A first phase error detecting portion (M2; 74, 86, 88, 94) detects a phase error which is a phase difference between the reproduced clock signal and the reference clock signal. A servo signal generating portion (M3; 50, 54, 58, 60, 96, 98, 100, 64) generates a servo signal which is used for eliminating the speed error and phase error. A second phase error detecting portion (M4; 114, 120) detects a phase error which is a phase difference between a reproduced synchronization signal reproduced from the recording medium separately from the reproduced clock signal and a reference synchronization signal. A reference phase changing portion (M5; 72, 70) changes the phase of the reference clock signal based on the phase error detected by the second phase error detecting portion. A reference frequency changing portion (M6; 130, 46) changes the frequency of the reference clock signal based on the phase error detected by the second phase error detecting portion.

    摘要翻译： 一种伺服电路，包括用于检测速度误差的速度误差检测装置（1044,1050），所述速度误差是从记录介质再现的再生时钟信号与基准时钟信号之间的频率差; 用于检测相位误差的相位误差检测装置（1078,1084,1092），所述相位误差是再现的时钟信号和参考时钟信号之间的相位差; 以及用于产生用于消除速度误差和相位误差的伺服信号的伺服信号产生装置（1052,1054,1057,1058,1060,1094,1046），其中所述相位误差检测装置包括：第一和第二分频 用于分别对再现的时钟信号和参考时钟信号进行分频的装置（1078,1048），其特征在于，分频比根据所述速度误差检测装置的速度误差增益的变化而改变; 以及用于检测分频再生时钟信号和分频基准时钟信号之间的相位误差的相位比较装置（1092）。