-
公开(公告)号：EP4441888A1
公开(公告)日：2024-10-09
申请号：EP22843459.3
申请日：2022-11-21
申请人： Qorvo US, Inc.
发明人： SCOTT, Baker , WOO, Chong , MAXIM, George
CPC分类号： H03F1/0272 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/45120130101 , H03F2200/10220130101
-
62.发明公开
公开(公告)号：EP4440019A3
公开(公告)日：2024-10-09
申请号：EP24167054.6
申请日：2024-03-27
申请人： Viavi Solutions Inc.
发明人： DIZDAR, Onur , BROWN, Matthew David , HOU, Jiancao , LEUNG, Chi-ming , SATTARZADEH HASHEMI, Ata , YAP, Yi Xien
IPC分类号： H04L1/00 , H03M13/13 , H03M13/00 , H04W72/232
CPC分类号： H04L1/0057 , H04L1/0071 , H03M13/13 , H04L1/0067 , H04L1/0052 , H03M13/635 , H04L1/0072
摘要： A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.
-
公开(公告)号：EP4366163A3
公开(公告)日：2024-10-09
申请号：EP23207140.7
申请日：2023-10-31
申请人： MediaTek Inc.
CPC分类号： H03F3/45475 , H03F3/195 , H03F2203/4554420130101 , H03F2203/4555120130101 , H03F2203/4558620130101 , H03F3/45932 , H03F2203/4508420130101 , H04L25/0276
摘要： A differential all-pass coupling circuit with common mode feedback is disclosed. An example apparatus includes an anti-aliasing circuit configured to reduce a bandwidth of a first differential signal, and a switched-capacitor circuit coupled to the anti-aliasing circuit configured to control a first switch to charge a capacitor to a first voltage based on a first difference between (i) a common mode input voltage associated with a first common mode voltage of the first differential signal and (ii) a common mode reference voltage associated with a second common mode voltage of an input stage of the receiver, control a second switch to provide a second voltage to the capacitor based on a second difference between the first differential signal and the common mode input voltage, and output a second differential signal to the input stage based on the first differential signal adjusted by the second voltage.
-
公开(公告)号：EP4220957B1
公开(公告)日：2024-10-09
申请号：EP23162193.9
申请日：2017-03-21
IPC分类号： H03H7/40 , H03H7/01 , H05H1/46 , H03F1/32 , H03F3/20 , H01J37/32 , H03F1/56 , H03F3/189 , H03H11/28
CPC分类号： H03F1/56 , H03F3/189 , H03F2200/45120130101 , H01J37/32183 , H03H11/28 , H03F1/32 , H03F3/20 , H03F2200/38720130101 , H03F2200/54120130101
-
65.发明授权
公开(公告)号：EP4149002B1
公开(公告)日：2024-10-09
申请号：EP22191627.3
申请日：2022-08-23
CPC分类号： H03K17/9622 , H03K17/9629 , H03K2217/9606620130101 , F24C7/086 , F24C7/083
-
公开(公告)号：EP4044004B1
公开(公告)日：2024-10-09
申请号：EP20875458.0
申请日：2020-10-09
IPC分类号： G06F3/02 , G06F3/042 , G06F3/04886 , H03K17/94 , G06F1/16 , G06F1/3215 , G06F1/3231 , G06F1/3234 , G06F1/3293 , H03K17/975 , H10K59/80
CPC分类号： G06F3/042 , G06F1/3293 , G06F1/3262 , G06F1/3265 , G06F1/3215 , G06F1/3231 , G06F1/1652 , G06F1/1671 , H03K2217/965320130101 , H03K2217/965520130101 , H03K2217/965620130101 , H03K2217/965120130101 , H03K17/975 , H10K59/879
-
公开(公告)号：EP3971932B1
公开(公告)日：2024-10-09
申请号：EP20198265.9
申请日：2020-09-25
-
-
公开(公告)号：EP4439976A1
公开(公告)日：2024-10-02
申请号：EP24165579.4
申请日：2024-03-22
摘要： La présente description concerne un dispositif électronique (200) configuré pour appliquer une fonction de décalage fréquentiel à un premier signal (Clk_F) ayant une première fréquence (F) comprenant :
- un élément à retard (206) adapté à fournir un deuxième signal (Clk_F_D) correspondant au premier signal retardé d'une durée égale à une première période dudit premier signal (Clk_F) divisée par quatre ;
- une branche comprenant successivement un premier circuit (201) adapté à diviser la fréquence d'un signal par un nombre, un deuxième circuit intégrateur (203), ladite branche étant adaptée à fournir un troisième signal (Q_comp) et un quatrième signal (I_comp) ; et
un troisième circuit mélangeur à bande latérale unique (208).-
70.发明公开
公开(公告)号：EP4439555A1
公开(公告)日：2024-10-02
申请号：EP23165194.4
申请日：2023-03-29
CPC分类号： H03M7/3059 , G06N3/045 , G10L21/02 , G10L25/30 , G10L21/0208 , G10L2021/0208220130101 , G10L21/038 , H03M7/3066
摘要： An apparatus for processing an information signal, comprises: a feature extractor (100) for extracting a set of features from the information signal, wherein the feature extractor (100) comprises: a raw feature calculator (110) for calculating raw feature results, each raw feature result having at least two raw feature components; and a raw feature compressor (120) for performing a compression of a dynamic range to the at least two raw feature components to obtain at least two compressed raw feature components for each raw feature result, wherein the set of features comprises the compressed raw feature components; and a signal processor (600) for processing the set of features to obtain the processed information signal, wherein the information signal comprises an audio signal, an image signal, or a radar signal.
-
-
-
-
-
-
-
-
-
搜索结果
109526 条记录 (耗时 0.058 秒)
