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    Schaltung und Verfahren zum Betrieb eines Knotens in einem Funknetz
    72.
    发明公开
    Schaltung und Verfahren zum Betrieb eines Knotens in einem Funknetz 审中-公开

    公开(公告)号：EP2265083A3

    公开(公告)日：2014-02-19

    申请号：EP10006049.0

    申请日：2010-06-11

    申请人： Atmel Corporation

    发明人： Ferchland, Tilo, Dipl.-Ing. ,  Walter, Udo ,  Schneider, Soeren

    IPC分类号： H04W52/02

    CPC分类号： H04W56/001 ,  H04L45/74 ,  H04W52/0206 ,  H04W88/025 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146

    摘要： Schaltung und Verfahren zum Betrieb eines Knotens in einem Funknetz, wobei Knoten desselben Funknetzes eine gemeinsame Netzkennung (NWID) und jedem Knoten individuell eine Knotenkennung (KNID) zugeordnet ist,
    - bei dem während des Empfangs eines aktuellen Pakets (100) durch eine Empfangsschaltung (310) des Knotens eine im Paket (100) enthaltene Adresse (160) ermittelt wird,
    - bei dem ein Empfang des aktuellen Pakets (100) fortgesetzt wird, wenn die ermittelte Adresse (160) mit der Netzkennung (NWID) des Knotens und der Knotenkennung (KNID) des Knotens übereinstimmt,
    - bei dem während des Empfangs des aktuellen Pakets (100) der Empfang des aktuellen Pakets abgebrochen und anhand einer Fallentscheidung die Empfangsschaltung (310) gesteuert wird, wenn die ermittelte Adresse (160) mit der Netzkennung (NWID) des Knotens oder der Knotenkennung (KNID) des Knotens nicht übereinstimmt.

    摘要翻译： 该方法涉及将相同无线电网络的节点分配为公共网络标识符，其中每个节点被单独分配节点标识符。 在通过节点的接收电路（310）接收当前分组时确定包中包含的地址。 当确定的地址与节点的网络标识符和节点的节点标识符匹配时，继续接收当前分组。 无线网络中的节点的电路还包括独立的权利要求。

    LOW VOLTAGE CIRCUIT FOR INTERFACING WITH HIGH VOLTAGE ANALOG SIGNALS
    73.
    发明授权
    LOW VOLTAGE CIRCUIT FOR INTERFACING WITH HIGH VOLTAGE ANALOG SIGNALS 有权
    低压电路具有高电压模拟连接信号

    公开(公告)号：EP1639701B1

    公开(公告)日：2011-11-02

    申请号：EP04753501.8

    申请日：2004-05-27

    申请人： ATMEL CORPORATION

    发明人： DUPUY, Christian ,  AMRANI, Hafid ,  CORDONNIER, Hubert

    IPC分类号： H03F3/45

    CPC分类号： G01R15/146 ,  H03F3/21 ,  H03F3/45475

    摘要： An integrated circuit (IC) uses a current source (420) coupled to means (460) for current-to voltage conversion to reject the unwanted high voltage signal (VHV,) and detect the wanted small voltage signal (VSENSE). In particular, the current source produces mirrored currents (I2, I3) proportional to the high voltage signal, while the means for converting current to-voltage rejects the common-mode current ( I2-I3) when there is no small signal voltage flowing through a sensing resistor (414). On the other hand, when the small signal voltage exists, a current flows across the sensing resistor and disturbs the balance of the current mirror. As a result, the common mode no longer exists and the means for converting current-to-voltage converts and amplifies this small signal current into a voltage (VOUT) proportional to the small voltage signal.

    Combined polynomial and natural multiplier architecture
    76.
    发明公开
    Combined polynomial and natural multiplier architecture 审中-公开
    Kombinierte Polynome undNatürlicheMultiplikatorarchitektur

    公开(公告)号：EP2138931A1

    公开(公告)日：2009-12-30

    申请号：EP09012998.2

    申请日：2004-03-22

    申请人： ATMEL CORPORATION

    发明人： Dupaquis, Vincent ,  Paris, Laurent

    IPC分类号： G06F7/72 ,  G06F7/52

    CPC分类号： G06F7/5318 ,  G06F7/724

    摘要： An integrated circuit parallel multiplication circuit delivers both natural multiplication products and polynomial products with coefficients over GF(2). The parallel multiplier hardware architecture ( Fig. 3 ) arranges the addition of partial products (Pi, j) so that it begins in a first group of adder stages (23) that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms (e k+1 ) is deferred until a second group of adder stages (29) is arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product (d k ) to be extracted from the results (s k ) of the first group of additions, and the natural product (c k ) to be extracted from the results of the second group of additions.

    摘要翻译： 集成电路并行乘法电路提供GF（2）上的系数的自然乘积和多项式乘积。 并行乘法器硬件体系结构（图3）排列了部分乘积（Pi，j）的加法，使得它开始于第一组加法器级（23），它们在不接收任何进位项作为输入的情况下执行加法， 的进位项（e k + 1）被推迟直到第二组加法器级（29）被布置成跟随第一组。 将加法器有意排列成两个单独的组允许从第一组添加的结果（sk）中提取多项式乘积（dk），并且从第二组的结果中提取天然产物（ck） 一组添加。

    ZERO POWER POWER-ON-RESET CIRCUIT
    78.
    发明授权
    ZERO POWER POWER-ON-RESET CIRCUIT 有权
    性能LOSE快速上电复位电路

    公开(公告)号：EP1034619B1

    公开(公告)日：2008-11-26

    申请号：EP98958071.7

    申请日：1998-11-20

    申请人： ATMEL CORPORATION

    发明人： PATHAK, Jagdish ,  PATHAK, Saroj ,  ROSENDALE, Glen, A. ,  PAYNE, James, E. ,  HANGZO, Nianglamching

    IPC分类号： H03K17/22

    CPC分类号： H03K17/223

    摘要： A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

    REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
    79.
    发明公开
    REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS 审中-公开
    而交错掺杂物质区域定位标记

    公开(公告)号：EP1922747A2

    公开(公告)日：2008-05-21

    申请号：EP06800557.8

    申请日：2006-07-28

    申请人： ATMEL CORPORATION

    发明人： DIETZ, Franz ,  DUDEK, Volker ,  GRAF, Michael ,  SCHWANTES, Stefan ,  MILLER, Gayle, W.

    IPC分类号： H01L21/30 ,  H01L21/76 ,  H01L23/544 ,  H01L27/01

    CPC分类号： G03F7/70425 ,  G03F7/70633 ,  G03F9/7076

    摘要： A registration mark, in integrated circuit technology, is formed by a first etching of a first mask layer (205) on top of an ONO stack (120, 125, 130) . After a first region (210) is doped, a second etching occurs at first etching sites (305) in the uppermost oxide layer (130) of the ONO stack forming a first alignment artifact (510b) . A second mask layer (405) is applied after removing the first mask layer. A second doping (515) occurs at second mask layer etching sites (510a) to maintain clearance between the two doped regions (210, 515) within active areas and provide an overlap (520) of the two doped regions in a frame area. At the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon (605) from the upper most layer of the semiconductor forming a second registration mark (710) , which may be covered by a protective layer (720) .

    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
    80.
    发明公开
    REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION 审中-公开
    具有低电场DMOS具有自对准抓斗ISOLATION

    公开(公告)号：EP1911095A2

    公开(公告)日：2008-04-16

    申请号：EP06786800.0

    申请日：2006-07-10

    申请人： Atmel Corporation

    发明人： MILLER, Gayle, W., Jr. ,  DUDEK, Volker ,  GRAF, Michael

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

    摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.