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公开(公告)号：EP3324546A1
公开(公告)日：2018-05-23
申请号：EP17197339.9
申请日：2017-10-19
申请人： NXP B.V.
CPC分类号： G01R33/096 , H03M3/422 , H03M3/462 , H03M3/464
摘要： A resistive sensor includes a current input sigma-delta converter that uses a switched offset voltage source to provide scalable gain and more linear operation. The sigma-delta converter includes an integrator, a quantizer, and a decimator. In one embodiment, the resistive sensor and offset voltage source are coupled to provide an input current at a first node. The integrator has a first input terminal coupled to the first node, and an output terminal. The quantizer has a first input terminal coupled to the output terminal of the integrator, a second input terminal for receiving a clock signal, and an output terminal coupled to provide a feedback signal to control the offset voltage source. The decimator has an input terminal coupled to the output terminal of the quantizer, and an output terminal for providing an output signal. The switched offset voltage source provides scalable gain and good linearity.
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公开(公告)号：EP2860875A1
公开(公告)日：2015-04-15
申请号：EP13187912.4
申请日：2013-10-09
申请人： NXP B.V.
IPC分类号： H03M3/00
摘要： An analogue to digital converter comprises an input terminal configured to receive an analogue input signal and an output terminal configured to provide an output digital signal. The analogue to digital converter also comprises a main summer having a summing input, a subtracting input and a summing output, wherein the summing input is connected to the input terminal; an analogue filter having a filter input and a filter output, wherein the filter input is connected to the summing output; a quantizer having a quantizer input and a quantizer output, wherein the quantizer input is connected to the filter output;a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator output is configured to provide a multi-bit output signal, the digital integrator input is connected to the quantizer output, and the digital integrator output is connected to the output terminal; and a main feedback digital to analogue converter having a main feedback converter input and a main feedback converter output, wherein the main feedback converter input is connected to the digital integrator output, and the main feedback converter output is connected to the subtracting input of the main summer.
摘要翻译： 模数转换器包括被配置为接收模拟输入信号的输入端和配置成提供输出数字信号的输出端。 模数转换器还包括具有加法输入，减法输入和求和输出的主加法器，其中求和输入连接到输入端; 具有滤波器输入和滤波器输出的模拟滤波器，其中所述滤波器输入连接到所述求和输出; 具有量化器输入和量化器输出的量化器，其中所述量化器输入连接到所述滤波器输出;具有数字积分器输入和数字积分器输出的数字积分器，其中所述数字积分器输出被配置为提供多位输出 信号，数字积分器输入连接到量化器输出，数字积分器输出连接到输出端; 以及具有主反馈转换器输入和主反馈转换器输出的主反馈数模转换器，其中主反馈转换器输入连接到数字积分器输出，并且主反馈转换器输出连接到主反馈转换器输入的减法输入 夏季。
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3.发明公开APPARATUS AND METHOD FOR PROVIDING INTERFACE BETWEEN MODEM AND RF CHIP 审中-公开设备和方法提供了一个接口之间的调制解调器和射频芯片
公开(公告)号：EP2789102A1
公开(公告)日：2014-10-15
申请号：EP12856144.6
申请日：2012-12-04
发明人： LEE, Jong-Woo
摘要： An Analog-Digital Converter (ADC) is provided. The ADC includes a plurality of sigma-delta modulators, a plurality of decimators, a plurality of differentiators, and a plurality of XOR operators. The plurality of sigma-delta modulators respectively convert analog signals to digital pulses. The plurality of decimators respectively convert a first sampling rate of a corresponding digital pulse to a second sampling rate which is lower than the first sampling. The plurality of differentiators respectively differentiate signals converted at the second sampling rate to perform delta modulation. The plurality of XOR operators extract a signal component changing with respect to the delta-modulated signals. Therefore, the number of interface pins between a modem and an RFIC can be reduced.
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4.发明公开
公开(公告)号：EP1407589A4
公开(公告)日：2004-09-29
申请号：EP02744551
申请日：2002-06-25
申请人： MOTOROLA INC
发明人： MARTIN FREDERICK L
IPC分类号： H03M3/00 , H04L27/233 , H04L27/14 , H04L27/06
CPC分类号： H04L27/2332 , H03M3/40 , H03M3/462
摘要： A digital IF to base band demodulator (120) includes delta sigma samplers (202, 204) for sampling two channels of an IF signal at a sampling rate that is substantially higher than the Nyquist rate for the IF signal. A first pair of decimation filters (206, 208) decimates and filters the output of the delta sigma samplers (202, 204) but keeps the samples at a rate sufficient to perform digital mixing, cross adding, and pulse shape match filtering. A set of mixers (210, 212, 214, 216) mixers the output of the first pair of decimation filters with two phases of a digital representation of an local IF signal. A pair of summers (222, 224) sums, and subtracts outputs of the set of mixers (210, 212, 214, 216) in order to cancel undesired harmonics. A second set of decimation filters (226, 228) decimates and filters the output of the summers (222, 224) applying a filter function that is matched to a pulse shape of a base band signal present in the IF signal.
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公开(公告)号：EP1046232A1
公开(公告)日：2000-10-25
申请号：EP99903040.6
申请日：1999-01-11
IPC分类号： H03M3/02
摘要： A noise cancellation circuit and quadrature downconverter for use in conjunction with a bandpass receiver. The noise cancellation comprises at least one bandpass decimator and a summer. The output from each loop of a sigma-delta analog-to-digital converter (ΣΔ ADC) is provided to a respective bandpass decimator. Each bandpass decimator comprises an error cancellation filter, a bandpass filter, and a decimator. The transfer functions of the error cancellation filter and bandpass filter are convolved to provide the transfer function of the bandpass decimator. The filtered signal is then decimated by N. The decimation by N can be incorporated within the bandpass decimator such that the bandpass decimator operates at 1/N of the frequency of the ADC sampling clock. The signals from all bandpass decimators are summed together and the resultant IF samples are provided to two multipliers which downconvert the IF samples to I and Q baseband samples with an inphase and a quadrature sinusoid, respectively. The baseband samples are lowpass filtered to further remove quantization noise and undesirable signals. The center frequency of the analog input signal, the ADC sampling clock, and the decimation by N can be selected such that an image of the input signal appears at 0.25fs, where fs is the sample rate of the decimated samples.
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公开(公告)号：EP0573409A1
公开(公告)日：1993-12-15
申请号：EP91900772.0
申请日：1990-12-19
CPC分类号： H03D1/2245 , H03D3/006 , H03D3/007 , H03D2200/005 , H03D2200/0054 , H03D2200/006 , H03M3/40 , H03M3/452 , H03M3/454 , H03M3/462
摘要： Dans le cas du convertisseur analogique-numérique interpolatif pour signaux de passe-bande selon l'invention, la quantification d'amplitudes des valeurs de balayage est effectuée dans 2 étages placés en série, le premier étage comprenant l'interface analogique-numérique proprement dite, et le second étage étant purement numérqiue. La quantification d'amplitudes des valeurs de balayage ne se fait pas ici, comme dans le cas des autres procédés, en utilisant des éléments finement quantifiés sur l'interface analogique-numérique, mais elle se fait par surbalayage, formation spectrale du bruit de quantification et interpolation numérique. Ceci permet d'utiliser sur l'interface analogique-numérique proprement dite des éléments à très basse définition (dans le cas extrême seulement avec 2 étages de quantification).
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公开(公告)号：EP0199745A1
公开(公告)日：1986-11-05
申请号：EP85904770.0
申请日：1985-09-24
发明人： ADAMS, Robert, W.
CPC分类号： H03H17/0621 , H03H17/0664 , H03M3/424 , H03M3/456 , H03M3/462
摘要： Un dispositif est utilisé pour convertir un signal d'entrée en un signal numérique de sortie à une fréquence présélectionnée d'échantillonnage avec une augmentation de la plage dynamique sans provoquer de crénelage. Le mode préféré de réalisation utilise un convertisseur (104) pour produire un signal numérique de basse résolution à une haute fréquence, et un agencement de filtre numérique (106) d'établissement de moyenne pour augmenter la résolution à la fréquence présélectionnée d'échantillonnage. Le dispositif peut produire aisément des signaux numériques de sortie d'au moins 17 bits, à une fréquence, par exemple, de 48KHZ.
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8.发明授权
公开(公告)号：EP1646151B1
公开(公告)日：2018-07-11
申请号：EP04735485.7
申请日：2004-05-31
发明人： BLASCO CLARET, Jorge Vicente , RIVEIRO INSUA, Juan Carlos , IRANZO MOLINERO, Salvador , GARCIA SAN JOSE , Aitor
摘要： The procedure carries out a resampling (25) in reception of a band-pass signal in which the signal is translated (4) to base-band with a configurable frequency and the resulting base-band signal is introduced into a decimator (5). Likewise, a resampling is carried out in transmission (26) where the base-band signal is interpolated (10) in order to be later on translated to band-pass (20) with a configurable frequency. The procedure permits correction of the frequency error introduced by digital-analog (11) and analog-digital (1) converters. Moreover, the proposed unit made up of band translation and resampling permits the complexity of the interpolation filters used for generating new samples of the digital signal to be simplified.
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9.发明公开
公开(公告)号：EP3307163A1
公开(公告)日：2018-04-18
申请号：EP16806476.4
申请日：2016-06-09
发明人： SOLTANI, Nima , GENOV, Roman
IPC分类号： A61B5/1468 , A61B5/1473 , H03M1/12 , H03M3/02
CPC分类号： A61B5/1473 , A61B5/002 , A61B5/0536 , A61B5/14532 , A61B5/14546 , A61B5/1477 , A61B5/4094 , A61B5/6868 , A61B5/7225 , A61B2560/0219 , H03M3/43 , H03M3/462 , H03M3/464
摘要： Systems, methods and apparatuses described herein generally provide a millimetre size package-free complementary metal-oxide-semiconductor (“CMOS”) chip (referred to as a “die”) for the in situ (on-site) measurement or imaging of electrochemically detectable analytes.
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公开(公告)号：EP2694921B1
公开(公告)日：2016-07-13
申请号：EP12716308.7
申请日：2012-04-05
发明人： DÜSTERBERG, Dirk
CPC分类号： G01D5/2073 , H03M1/645 , H03M3/462
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