公开(公告)号：EP4390707A1

公开(公告)日：2024-06-26

申请号：EP23195422.3

申请日：2023-09-05

Applicant: INTEL Corporation

Inventor： RAKSHIT, Joydeep ,  NORI, Anant Vithal ,  SUBRAMONEY, Sreenivas ,  ALAM, Hanna ,  NUZMAN, Joseph

IPC: G06F12/084 ,  G06F12/1009

CPC classification number: G06F12/084 ,  G06F12/1009

Abstract: Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.

公开(公告)号：EP3783480B1

公开(公告)日：2024-04-24

申请号：EP19819486.2

申请日：2019-03-28

IPC: G06F9/38 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/1036 ,  G06F12/14 ,  G06F12/084 ,  G06F12/0842 ,  G06F3/06 ,  G06F12/1045 ,  G06F12/0895 ,  G06F9/455

CPC classification number: G06F2212/102420130101 ,  G06F12/1491 ,  G06F12/0871 ,  G06F12/0868 ,  G06F2212/60120130101 ,  G06F12/0897 ,  G06F2212/31120130101 ,  G06F2212/31320130101 ,  G06F12/0292 ,  G06F2212/65120130101 ,  G06F2212/15120130101 ,  G06F12/1036 ,  G06F12/0842 ,  G06F12/084 ,  G06F2009/4558320130101 ,  G06F2009/4557920130101 ,  G06F3/067 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/061 ,  G06F12/1063

公开(公告)号：EP4352622A1

公开(公告)日：2024-04-17

申请号：EP22741078.4

申请日：2022-06-08

Applicant: Ampere Computing LLC

Inventor： SHANNON, Richard James ,  JOURDAN, Stephan Jean ,  ERLER, Matthew Robert ,  BENDT, Jared Eric

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/254220130101 ,  G06F2212/604220130101

公开(公告)号：EP3797359B1

公开(公告)日：2024-04-17

申请号：EP19810228.7

申请日：2019-05-31

IPC: G06F12/0811 ,  G06F9/38 ,  G06F12/084 ,  G06F12/0804 ,  G06F12/0817 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0895

CPC classification number: G06F12/0895 ,  G06F12/0811 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F2201/8220130101 ,  G06F2201/80520130101 ,  G06F2201/88520130101 ,  G06F11/3024 ,  G06F11/3037 ,  G06F2212/103220130101 ,  G06F2212/100820130101 ,  G06F12/084 ,  G06F12/0804 ,  G06F12/0828 ,  Y02D10/00

公开(公告)号：EP3394723A1

公开(公告)日：2018-10-31

申请号：EP16879667.0

申请日：2016-11-18

Applicant: Intel Corporation

Inventor： OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F9/345 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30101 ,  G06F9/3016 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452

Abstract: A processor includes an execution unit to execute lane-based strided scatter instructions. The execution unit includes logic to extract a first data element from each of multiple lanes within a source vector register and to extract a second data element from each lane. The execution unit includes logic to place, in a destination vector, the first data element extracted from the second lane next to the first data element extracted from the first lane, and the second data element extracted from the second lane next to the second data element extracted from the first lane. The execution unit includes logic to store each collection of data elements placed next to each other in the destination vector in contiguous locations beginning at an address computed from a base address and a respective element of an index register specified in the instruction. Each collection of data elements represents a data structure.

公开(公告)号：EP3388947A1

公开(公告)日：2018-10-17

申请号：EP17192502.7

申请日：2014-10-22

Applicant: Huawei Technologies Co., Ltd.

Inventor： LIU, Lei ,  WU, Chengyong ,  FENG, Xiaobing

IPC: G06F12/08 ,  G06F11/34 ,  G06F3/06 ,  G06F12/00 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0897

CPC classification number: G06F3/0605 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/5016 ,  G06F11/3409 ,  G06F11/3433 ,  G06F11/3471 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0897 ,  G06F2201/81 ,  G06F2212/1041 ,  G06F2212/282 ,  G06F2212/6042 ,  G06F2212/653

Abstract: Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a storage resource in light of a feature of the working set, thereby improving overall performance of a computer.

公开(公告)号：EP3049940B1

公开(公告)日：2018-09-19

申请号：EP14783720.7

申请日：2014-09-23

Applicant: Microsoft Technology Licensing, LLC

Inventor： STAIRS, John ,  KRISTOFFERSEN, Esben Nyhuus ,  HEJLSBERG, Thomas

IPC: G06F12/123 ,  G06F12/122 ,  G06F12/084 ,  G06F12/0866

CPC classification number: G06F12/122 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/123 ,  G06F2212/601

Abstract: A cache manager application provides a data caching policy in a multiple tenant enterprise resource planning (ERP) system. The cache manager application manages multiple tenant caches in a single process. The application applies the caching policy. The caching policy optimizes system performance compared to local cache optimization. As a result, tenants with high cache consumption receive a larger portion of caching resources.

公开(公告)号：EP3309685A4

公开(公告)日：2018-07-25

申请号：EP16843508

申请日：2016-06-29

Applicant: HUAWEI TECH CO LTD

Inventor： HUANG FUTANG

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/08 ,  G06F12/084 ,  G06F2212/222 ,  G06F2212/604

Abstract: A method and an apparatus for writing data into a cache are provided. The method includes: receiving an IO request write command, where the IO request write command includes metadata of to-be-written data; obtaining a first buddy group from a global buddy queue, and determining whether all metadata of the to-be-written data can be written into the first buddy group; and if yes, writing all the metadata of the to-be-written data into the first buddy group, and writing all the metadata of the to-be-written data into a metadata block corresponding to a metadata group to which the first buddy group belongs. Therefore, a problem that a lifetime of a flash is affected because the metadata is frequently written into the flash can be resolved.

公开(公告)号：EP3230850A4

公开(公告)日：2018-06-20

申请号：EP15868111

申请日：2015-12-10

Applicant: ALIBABA GROUP HOLDING LTD

Inventor： MA LIN ,  ZHOU WEI ,  ZHANG LEI

IPC: G06F9/00 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F13/16

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/621

Abstract: A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.

公开(公告)号：EP3121684B1

公开(公告)日：2018-05-02

申请号：EP14897637.6

申请日：2014-07-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： YANG, Tongzeng ,  WEI, Konggang ,  PENG, Yu

IPC: G06F1/32 ,  G06F12/084 ,  G06F12/0897 ,  G06F1/08 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F12/084 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172

Abstract: The present invention discloses a method for managing a multi-core processor. The method includes: if a current working mode of the multi-core processor is an asymmetric multiprocessing ASMP mode, a working frequency of at least one other processor than one processor that requests data is less than a first frequency, and a difference between a cache hit ratio value corresponding to the one processor and a cache hit ratio value corresponding to the at least one other processor is greater than or equal to a first threshold, switching the working mode of the multi-core processor to a symmetric multiprocessing SMP mode; or if a current working mode of the multi-core processor is an SMP mode, a cache hit ratio value corresponding to the one processor is greater than or equal to a second threshold, usage rates are unbalanced between processors in the multi-core processor, and usage rates of N processors in the multi-core processor are greater than a first usage threshold, switching the working mode of the multi-core processor to an ASMP mode, where N is greater than or equal to 1, and is less than or equal to a quantity of processors in the multi-core processor minus one.