公开(公告)号：EP0173744A4

公开(公告)日：1988-04-27

申请号：EP85901763

申请日：1985-03-14

申请人： MOORE DONALD W ,  VERSTRAETE RIK A

发明人： MOORE DONALD W

IPC分类号： G06F11/20 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733 ,  H03K19/003 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17764

摘要： A programmable gate structure (20) having functionally redundant architeture for enhanced production yields and reliability comprises a plurality of two-input nodes (10) at least some of which may be programmed by control states (24, 26 and 28) for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for reprogramming in response to detected faults to achieve a desired gate function. A number of embodiments are disclosed including selected architectural simplifications wherein certain nodes in a network are logically fixed to reduce the number of control lines. Illustrative computer programs for generating the proper control line signals for a selected gate function in such embodiments are disclosed.

公开(公告)号：EP0194091A3

公开(公告)日：1987-12-16

申请号：EP86301338

申请日：1986-02-25

申请人： LATTICE SEMICONDUCTOR CORPORATION

发明人： Turner, John E.

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17764 ,  H03K19/1778

摘要： A programmable logic device is disclosed which is adapted to isolate the Miller capacitances of erased memory cells from the product terms and to limit the cell current drawn through the product term sense amplifiers. The invention substantially reduces the row switching noise coupled onto the product terms, allows high speed sense amplifier operation, and significantly reduces the power dissipated by the device. In accordance with the invention, the electrically erasable sense transistor M2 for each memory cell is disposed between the cell select transistor M1 and the product term sense amplifier, thereby isolating the Miller. capacitance associated with the select transistor from the sense amplifier when the cell is in the erased (nonconductive) state. Separate product term ground lines 35 are provided for each product term 30. A current limiter connects each product term ground line to ground, and is adapted to limit the current flow through each product term to a predetermined maximum level, typically about the maximum current level which may be passed through one conductive memory cell.

公开(公告)号：EP0068374B1

公开(公告)日：1987-03-25

申请号：EP82105403.8

申请日：1982-06-19

申请人： Hewlett-Packard Company

发明人： Skokan, Zdenek Emil

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  Y10S257/923

公开(公告)号：EP0196771A2

公开(公告)日：1986-10-08

申请号：EP86301336.3

申请日：1986-02-25

申请人： LATTICE SEMICONDUCTOR CORPORATION

发明人： Turner, John E. ,  Rutledge, David L.

IPC分类号： H03K19/177 ,  G06F11/26

CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

摘要： An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) 30 which is coupled to the product terms of the PLD array 10. Input programming data for a selected row of the array is serially entered into the SRL 1 0, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array 10 may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL 30 in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

公开(公告)号：EP0099135A2

公开(公告)日：1984-01-25

申请号：EP83107041.2

申请日：1983-07-18

申请人： NEC CORPORATION

发明人： Ohmori, Kenji

IPC分类号： H03K19/173 ,  G06F15/20

CPC分类号： G06F7/76 ,  G06F17/5022 ,  H03K19/1733 ,  H03K19/17704

摘要： A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.

公开(公告)号：EP0098173A2

公开(公告)日：1984-01-11

申请号：EP83303805.2

申请日：1983-06-30

申请人： FUJITSU LIMITED

发明人： Sugiyama, Eiji ,  Saito, Toshiharu ,  Natsume, Mitsuaki

IPC分类号： H01L27/02 ,  H03K19/086

CPC分类号： H03K19/17736 ,  H01L27/11801 ,  H01L2924/14 ,  H03K19/00307 ,  H03K19/086 ,  H03K19/17704 ,  H03K19/17784 ,  H03K19/17796

摘要： A semiconductor integrated-circuit apparatus includes an electro-conductive layer (64, Figure 19) formed on a substrate, a plurality of internal cells (INC) formed on the electro-conductive layer, a plurality of bonding pads (BP) arranged around the internal cells, and a plurality of bias cells (SBC) which are common to the plurality of internal cells and which generate a predetermined voltage. A plurality of bias buffer circuits (INB) supply the predetermined voltage generated in the bias cells to the internal cells.

摘要翻译： 半导体集成电路装置包括形成在衬底上的导电层（64，图19），形成在导电层上的多个内部单元（INC），布置在导电层周围的多个接合焊盘（BP） 内部单元以及多个内部单元所共有的并产生预定电压的多个偏置单元（SBC）。 多个偏置缓冲电路（INB）将在偏置单元中产生的预定电压提供给内部单元。

公开(公告)号：EP0086646A1

公开(公告)日：1983-08-24

申请号：EP83300708.1

申请日：1983-02-11

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yamazaki, Isamu

IPC分类号： H03K19/177 ,  G06F7/50

CPC分类号： G06F7/5057 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778

摘要： A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.

公开(公告)号：EP0066729A1

公开(公告)日：1982-12-15

申请号：EP82104236.3

申请日：1982-05-14

申请人： International Business Machines Corporation

发明人： Hsieh, John Chyang ,  Wu, Wei-Wha

IPC分类号： G01R31/28 ,  G06F11/26 ,  H03K19/177

CPC分类号： G01R31/318516 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17764

摘要： A logic array (10) includes a matrix logical elements (13) located at the intersections of a plurality of input (16) and output lines (17). Due to the nature of the array structure, more than one output line (17) may be activated by a given digital bit pattern placed on the input lines (16). In testing the array, the lack of a one-to-one correspondence makes it difficult to determine if the personalization associated with a given output line is proper.
The output line interference problem is solved by providing a deletion control line (28) which may be selectively connected to any combination of output lines (17) to thereby disable the connected output lines. Thus, a given output line may be personalized, tested and then disabled, to preclude interference between the tested output line and the remainder of the lines to be tested. Moreover, since the logic array (10) is tested one line at a time, provision can be made for substituting spare output lines (17 E, F) for defective output lines, thereby rendering a defective array usable.

公开(公告)号：EP0020608A1

公开(公告)日：1981-01-07

申请号：EP79901588.0

申请日：1979-10-26

申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY

发明人： PATIL, Suhas S.

IPC分类号： G06F7 ,  G11C17 ,  H03K19

CPC分类号： G06F7/5057 ,  G11C17/00 ,  G11C17/14 ,  H03K19/17704

摘要： Dans une forme programmable (PSLA), la matrice comprend un ensemble de conducteurs en colonnes paralleles segmentables de maniere programmable et un ensemble orthogonal de conducteurs en ligne segmentables de maniere programmable. Chacun des reseaux de cellule de memoire est associe et accouple a un sous-ensemble de conducteurs en ligne et a un sous-ensemble de conducteurs en colonne. Au moins un sous-ensemble de conducteurs en colonne possede un reseau de cellules de memoire associees qui comprend un element de stockage qui est accouple au sous-ensemble de colonnes et au sous-ensemble de lignes associes pour ce reseau de cellules de memoire. Dans une forme non programmable, la matrice de stockage/logique (SLA) est semblable a la forme programmable (PSLA) si ce n'est que les conducteurs en lignes et en colonnes sont segmentes en des endroits predetermines, et que les reseaux de cellules de memoire sont accouples a des sous-ensembles predetermines associes de conducteurs en lignes et en colonnes.

摘要翻译： 在可编程形式（PSLA）中，矩阵包括一组可编程的可分段并行列导体和一组正交可编程的可分段线路导体。 每个存储器单元网络与线路驱动器的子集相关联并耦合，并且具有列导体的子集。 列导体的至少一个子集具有关联的存储器单元的网络，所述存储器单元的网络包括耦合到列的子集的存储元件以及用于该存储器单元网络的关联行的子集。 在不可编程的形式中，存储/逻辑阵列（SLA）类似于可编程形式（PSLA），除了线路和列导体在预定位置被分段以外，并且单元网络 连接到与行和列中的导体相关的预定子组件。

公开(公告)号：EP2541774A2

公开(公告)日：2013-01-02

申请号：EP12173626.8

申请日：2012-06-26

申请人： Samsung Electronics Co., Ltd.

发明人： Kim, Ho-jung ,  Shin, Jai-kwang ,  Choi, Hyun-sik ,  Jeong, Hyung-su

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

摘要： According to example embodiments, a logic device (20) includes a first functional block (21) configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block (22) configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block (21) is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block (22) is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.

摘要翻译： 根据示例实施例，逻辑设备（20）包括被配置为根据第一操作信息执行第一操作的第一功能块（21）和根据第二操作信息的第二操作;以及第二功能块（22），被配置为 根据第一操作信息和根据第二操作信息的第四操作执行第三操作。 第一功能块（21）被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作 。 第二功能块（22）被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作执行第三或第四操作 信息。