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    Static random access memory with address transition detector
    83.
    发明公开
    Static random access memory with address transition detector 失效
    统计员RAM-Speicher mit einemAdressenübergangsdetektor。

    公开(公告)号：EP0337202A2

    公开(公告)日：1989-10-18

    申请号：EP89105628.5

    申请日：1989-03-30

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Hayakawa, Shigeyuki c/o Patent Division ,  Matsui, Masataka c/o Patent Division

    IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C11/418

    CPC分类号： G11C8/18 ,  G11C7/062 ,  G11C7/12 ,  G11C11/418

    摘要： When an address transition detector (13) detects a transition of an address signal (Add), it produces an address transition detect signal (SATD). The signal (SATD) drives a bit line initializing circuit (6) which in turn initializes paired bit lines (5, 5 ), and ini­tializes the paired output lines (26, 26 ) of a sense amplifier (10). At the same time, a clock signal gener­ator (14) generates a clock signal (φS) for a predeter­mined period of time in accordance with the address transition detect signal (SATD). The clock signal (φS) is supplied to the sense amplifier (10) and a data out­put circuit (11). The sense amplifier (10) is active during a period that the clock signal (φS) from the clock signal generator (14) is in an effective level. The output terminal of the data output circuit (10) is placed in a high impedance state during the period that the clock signal (φS) is in an effective level. During the other periods than the effective level period, the data output circuit (11) produces a signal (Dout) corre­sponding to the data as is read out of a memory cell (7) and outputted by the sense amplifier (10).

    摘要翻译： 当地址转换检测器（13）检测到地址信号（Add）的转变时，产生地址转换检测信号（SATD）。 信号（SATD）驱动位线初始化电路（6），该位线初始化电路（6）进而初始化配对位线（5,5），并初始化读出放大器（10）的配对输出线（26,26）。 同时，时钟信号发生器（14）根据地址转换检测信号（SATD）产生预定时间段的时钟信号（phi S）。 时钟信号（phi S）被提供给读出放大器（10）和数据输出电路（11）。 在来自时钟信号发生器（14）的时钟信号（phi S）处于有效电平的时段期间，读出放大器（10）有效。 在时钟信号（phi S）处于有效电平的期间，数据输出电路（10）的输出端子处于高阻抗状态。 在与有效电平周期相比的其他周期期间，数据输出电路（11）产生与从存储单元（7）读出并由读出放大器（10）输出的数据对应的信号（Dout）。

    IMPROVED TIMING CIRCUIT FOR MEMORIES
    86.
    发明公开
    IMPROVED TIMING CIRCUIT FOR MEMORIES 审中-公开

    公开(公告)号：EP4213151A1

    公开(公告)日：2023-07-19

    申请号：EP23160026.3

    申请日：2017-06-07

    申请人： QUALCOMM Incorporated

    发明人： GHOSH, Sonia ,  JUNG, Changho

    IPC分类号： G11C7/22 ,  G11C7/08 ,  G11C11/418 ,  G11C11/419

    摘要： A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.