公开(公告)号：EP2822179B1

公开(公告)日：2019-05-01

申请号：EP14175120.6

申请日：2014-07-01

申请人： Azbil Corporation

发明人： Kajita, Tetsuya

IPC分类号： H03K17/14 ,  H03F3/72 ,  H05B37/02 ,  H03K17/16

公开(公告)号：EP3311487B1

公开(公告)日：2019-04-10

申请号：EP16725990.2

申请日：2016-05-13

申请人： Hella Corporate Center USA, Inc.

发明人： LU, Juncheng ,  BAI, Hua

IPC分类号： H03K17/12 ,  H03K17/16 ,  H03K17/13 ,  H03K17/284

公开(公告)号：EP3048715B1

公开(公告)日：2019-03-27

申请号：EP15152501.1

申请日：2015-01-26

申请人： NXP B.V.

发明人： Dikken, Jan ,  Kleinpenning, Jeroen

IPC分类号： H02M3/335 ,  H03K17/16 ,  H03K17/042 ,  H03K17/30

公开(公告)号：EP2660979B1

公开(公告)日：2019-02-27

申请号：EP12166206.8

申请日：2012-04-30

申请人： Dialog Semiconductor GmbH

发明人： Knoedgen, Horst

IPC分类号： H03K17/687 ,  H03K17/16

公开(公告)号：EP2873153B1

公开(公告)日：2019-02-13

申请号：EP13744735.5

申请日：2013-07-11

申请人： Valeo Systèmes De Contrôle Moteur

发明人： BOUCHEZ, Boris ,  GRENIER, Mathieu

IPC分类号： H03K17/082 ,  H03K17/16

公开(公告)号：EP3419169A2

公开(公告)日：2018-12-26

申请号：EP18171089.8

申请日：2018-05-07

申请人： Elmos Semiconductor Aktiengesellschaft

发明人： Sudhaus, Andre

IPC分类号： H03K17/06 ,  H03K17/16 ,  H02M1/08 ,  H02M1/32 ,  H02H3/087 ,  H01L27/092 ,  H02H9/00 ,  H03K17/0412

CPC分类号： H02H9/005 ,  H02H3/087 ,  H03K17/04123 ,  H03K17/063 ,  H03K2017/066 ,  H03K2217/0018

摘要： Die elektronische Sicherung für mindestens einen elektrischen Verbraucher ist versehen mit mindestens einem Unterbrechungs-Halbleiterschalter (12) und einem Treiber (16) für den Unterbrechungs-Halbleiterschalter (12). Der Treiber (16) ist versehen mit einem Highside-Schalter (20), der zwischen einem Versorgungspotential (V 1 ) und dem Ausgangsanschluss (28) des Treibers (16) geschaltet ist, und mit einer zwischen dem Ausgangsanschluss (28) und Masse (42) geschalteten Einheit (40) zur zwecks Öffnen des Unterbrechungs-Halbleiterschalters (12) erfolgenden Ableitung eines Stroms von der Ansteuerelektrode (14) des Unterbrechungs-Halbleiterschalters (12). Ferner beinhaltet die Vorrichtung mindestens eine Störunterdrückungs-Bauteilanordnung (SB) zur Verhinderung einer den Betrieb des Unterbrechungs-Halbleiterschalters (12) beeinträchtigenden und insbesondere ein ungewolltes Öffnen des Unterbrechungs-Halbleiterschalters (12) verursachenden Potentialveränderung, insbesondere Mittelwertverschiebung, am Ausgangsanschluss (28) des Treibers (16) als Folge von unsymmetrischen Reaktionen des Treibers (16) auf Störsignale, die über die Versorgungsleitung (34) des Verbrauchers einkoppelbar sind und/oder in der Versorgungsleitung (34) des Verbrauchers entstehen.

公开(公告)号：EP2822180B1

公开(公告)日：2018-09-12

申请号：EP12869891.7

申请日：2012-12-04

申请人： Fuji Electric Co., Ltd.

发明人： AKAHANE, Masashi

IPC分类号： H03K17/16 ,  H02M1/08 ,  H02M7/538 ,  H03K17/04 ,  H03K17/687 ,  H03K17/26 ,  H03K17/0412 ,  H03K17/0812 ,  H03K19/0185

CPC分类号： H03K19/018521 ,  H02M7/538 ,  H02M2001/0054 ,  H03K3/012 ,  H03K3/013 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/26 ,  H03K19/018528 ,  H03K2217/0063 ,  H03K2217/0081 ,  Y02B70/1491

摘要： With an object of reducing a delay in signal transmission by a circuit that prevents malfunction due to dV/dt noise of a high potential side switching element (XD1) configuring a half bridge, pulse generating means (40) that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.

公开(公告)号：EP3367567A1

公开(公告)日：2018-08-29

申请号：EP17158392.5

申请日：2017-02-28

申请人： Siemens Aktiengesellschaft

发明人： Rupp, Jürgen

IPC分类号： H03K17/0814 ,  H03K17/16

CPC分类号： H03K17/08148 ,  H03K17/162 ,  H03K17/168

摘要： Die Erfindung betrifft eine Schaltvorrichtung (1) zum Auftrennen eines quell- und lastseitige Induktivitäten (3, 5) umfassenden Strompfads (6) eines Gleichspannungsnetzes. Die Schaltvorrichtung (1) umfasst zumindest zwei in Serie verschaltete Schaltmodule (10), wobei jedes der Schaltmodule (10) zumindest ein steuerbares Halbleiterschaltelement (13, 16) umfasst, dem eine Serienschaltung aus einem Widerstand (14) und einem Kondensator (15) parallel geschaltet ist.

公开(公告)号：EP3346611A1

公开(公告)日：2018-07-11

申请号：EP18157696.8

申请日：2009-03-02

申请人： Peregrine Semiconductor Corporation

发明人： RANTA, Tero Tapio

IPC分类号： H03M1/80 ,  H01F21/12 ,  H01G4/002 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L49/02 ,  H03H7/01 ,  H03H7/38 ,  H03H11/28 ,  H03J3/20 ,  H03K17/16 ,  H03K17/687 ,  H03M1/10 ,  H03K17/10

CPC分类号： H03H11/28 ,  H01F21/12 ,  H01G4/002 ,  H01G7/00 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/60 ,  H03H7/0153 ,  H03H7/38 ,  H03J3/20 ,  H03J2200/10 ,  H03K17/102 ,  H03K17/162 ,  H03K17/687 ,  H03M1/1061 ,  H03M1/804

摘要： A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF- terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB. Each significant bit of the digital control word is coupled to corresponding and associated significant bit sub-circuits of the DTC, and thereby controls switching operation of the associated sub-circuit. DTCs are implemented using unit cells, wherein the LSB sub-circuit comprises a single unit cell. Next significant bit sub-circuits comprise x instantiations of the number of unit cells used to implement its associated and corresponding previous significant bit sub-circuit, wherein the value x is dependent upon a weighting coding used to weight the significant bit sub-circuits of the DTC. DTCs may be weighted in accordance with a binary code, thermometer code, a combination of the two, or any other convenient and useful code. In many embodiments, the unit cell comprises a plurality of stacked FETs in series with a capacitor. The unit cell may also include a plurality of gate resistors R G coupled to the gates of the stacked FETs, and a plurality of R DS resistors coupled across the drain and source of the stacked FETs. The stacked FETs improve the power handling capabilities of the DTC, allowing it meet or exceed high power handling requirements imposed by current and future communication standards.

公开(公告)号：EP3311412A1

公开(公告)日：2018-04-25

申请号：EP16812463.4

申请日：2016-06-16

申请人： Tagore Technology, Inc.

发明人： SHAH, Manish, N. ,  DAS, Amitava

IPC分类号： H01L29/66 ,  H01L29/15 ,  H03K17/16 ,  H03K17/687

CPC分类号： H03K17/063 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7831 ,  H03K2017/066 ,  H03K2017/6875 ,  H03K2217/0081

摘要： A HEMT cell includes two or more gallium nitride (“GaN”) high-electron-mobility transistor (“HEMT”) devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source, and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (“2DEG”) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.