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    CIRCUIT AND METHOD FOR READING A MEMORY CELL OF A NON-VOLATILE MEMORY DEVICE
    81.
    发明公开
    CIRCUIT AND METHOD FOR READING A MEMORY CELL OF A NON-VOLATILE MEMORY DEVICE 审中-公开
    用于读取非易失性存储器装置的存储器单元的电路和方法

    公开(公告)号：EP3217405A1

    公开(公告)日：2017-09-13

    申请号：EP16194682.7

    申请日：2016-10-19

    申请人： STMicroelectronics S.r.l.

    发明人： CAMPARDO, Giovanni ,  POLIZZI, Salvatore

    IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C16/24 ,  G11C16/28

    CPC分类号： G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2207/12

    摘要： A circuit (20) for reading a memory cell (3) of a nonvolatile memory device (1) provided with a memory array (2) with cells arranged in wordlines and bitlines, among which a first bitline (BL), associated to the memory cell, and a second bitline (BL'), has: a first circuit branch (22) associated to the first bitline and a second circuit branch (22') associated to the second bitline, each with a local node (N 1 , N 1 '), coupled to which is a first dividing capacitor (30), and a global node (N g , N g '), coupled to which is a second dividing capacitor (32); a decoder stage (23, 25) for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage (36), which has inputs that are coupleable to the global node of the first circuit branch or second circuit branch, and supplies an output signal (S out ) indicative of the datum stored; a coupling stage (40, 41), for coupling the global nodes of the first and second circuit branches; and a control unit (21) for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

    摘要翻译： 一种用于读取非易失性存储器件（1）的存储单元（3）的电路（20），所述非易失性存储器件（1）具有以字线和位线排列的存储单元（2） 单元和第二位线（BL'）具有：与第一位线关联的第一电路分支（22）和与第二位线关联的第二电路分支（22'），每个分支具有本地节点（N1，N1' ）耦合至第一分压电容器（30）和全局节点（Ng，Ng'），所述全局节点耦合至第二分压电容器（32）。 解码器级（23,25），用于将本地节点耦合到第一或第二位线并将全局节点耦合到本地节点; 和差分比较器级（36），其具有可耦合到第一电路分支或第二电路分支的全局节点的输入，并提供指示所存储的数据的输出信号（Sout）; 耦合级（40,41），用于耦合所述第一和第二电路分支的全局节点; 以及控制单元（21），用于控制解码器级，耦合级和差分比较器级以产生输出信号。

    Memory cell and memory array utilizing the memory cell
    82.
    发明授权
    Memory cell and memory array utilizing the memory cell 有权
    存储单元的存储单元和存储装置

    公开(公告)号：EP2490222B1

    公开(公告)日：2017-01-11

    申请号：EP12155499.2

    申请日：2012-02-15

    申请人： Nanya Technology Corporation

    发明人： Ting, Tah-Kang Joseph

    IPC分类号： G11C11/405 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

    CPC分类号： G11C11/405 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097

    摘要： A memory cell (100) having a first switch device (Tr1), a second switch device (Tr2) and a capacitor (C) is disclosed. The first switch device (Tr1) has a control terminal coupled to and controlled by a select line (SL), a first terminal coupled to a bit line (BL), and a second terminal. The second switch device (Tr2) has a first terminal coupled to the second terminal of the first switch device (Tr1), a control terminal coupled to and controlled by a word line (WL), and a second terminal. The capacitor (C) has a first terminal coupled to the second terminal of the second switch device (Tr2) and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor (C) or written to the capacitor (C) via the bit line (BL).

    SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, SOME INCLUDING HIERARCHICAL AND/OR OTHER FEATURES
    88.
    发明公开
    SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, SOME INCLUDING HIERARCHICAL AND/OR OTHER FEATURES 有权
    系统和多片位存储阵列的方法，一些与层次型和/或其它特征

    公开(公告)号：EP2788986A1

    公开(公告)日：2014-10-15

    申请号：EP12856183.4

    申请日：2012-12-10

    申请人： GSI Technology Inc.

    发明人： LEE, Hsin You, S. ,  TUNG, Chenming, W. ,  SHU, Leelean

    IPC分类号： G11C7/18

    CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/418 ,  H01L21/823475 ,  H01L27/1104

    摘要： A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

    摘要翻译： SRAM存储器装置具有层次结构划分出的位线的SRAM存储装置，以及相关的系统和方法的层次分段位线进行了描述。 在一个说明性实现中，每个分段位线可以包括本地的位线，连接到本地的位线的存储单元，以及耦合到所述局部位线上的通门，worin通门被配置为被耦合到全局位 线，并且所述worin分段位线被安排在分层阵列。 在其他实现中，分层SRAM存储器设备可以被配置涉及分段位线和全局位线的worin通门被构造成连接和分离切片位线和所述全局位线。