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    FLUID CONTROL VALVE ARRANGEMENT
    4.
    发明授权
    FLUID CONTROL VALVE ARRANGEMENT 失效
    流量控制阀

    公开(公告)号：EP0612387B1

    公开(公告)日：1997-09-17

    申请号：EP92912518.5

    申请日：1992-05-19

    申请人： PHOTOVAC INTERNATIONAL, INC.

    发明人： LEVESON, Richard, C. ,  BASSETT, Mark, D.

    IPC分类号： F16K7/12 ,  F16K7/17 ,  F15C3/04

    CPC分类号： G01N35/1097 ,  F16K7/17 ,  G01N30/20 ,  G01N2030/205 ,  Y10T137/87885

    摘要： A fluid control valve arrangement includes a plurality of clusters or pairs of holes extending from one face to the other of a central block (11). The valves (20) comprise a plurality of deformable blisters (12a) formed in a resilient membrane (12), the blisters (12a) positioned so as to coincide with the hole clusters or pairs when the membrane (12) is pressed against a face of the block. The valves are closed when the blisters are deformed to an essentially flat shape, advantageously by introducing a high pressure fluid into a cavity (14a) above the blisters (12a). The valves (20) are linked together in a desired configuration by grooves (11b) formed in the other face of the block (11).

    Testing of integrated circuits using clock bursts
    7.
    发明授权
    Testing of integrated circuits using clock bursts 失效
    测试使用的时钟颠簸集成电路。

    公开(公告)号：EP0435636B1

    公开(公告)日：1995-02-22

    申请号：EP90314196.8

    申请日：1990-12-21

    申请人： LSI LOGIC CORPORATION

    发明人： Walker, Robert M. ,  Liu, Dick L.

    IPC分类号： G06F11/26 ,  G01R31/28

    CPC分类号： G01R31/31937

    摘要： A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.

    Die casting using casting salt cores
    10.
    发明公开
    Die casting using casting salt cores 失效
    抹上盐芯压铸。

    公开(公告)号：EP0613742A1

    公开(公告)日：1994-09-07

    申请号：EP94301347.4

    申请日：1994-02-25

    申请人： PUGET CORPORATION

    发明人： Flessner, Thomas F. ,  Marr, Christopher S.

    IPC分类号： B22C9/10 ,  B22D17/24

    CPC分类号： B22C9/105

    摘要： A process of providing a disposable core for use in die casting processes. A salt material is molten and cast into a core of a desired configuration under exacting conditions. The fluidity of the molten salt is controlled enabling casting the salt material into a core by die casting methods. The die casting method provides a core with a high surface finish and strength. The core is evenly cooled subsequent to it being cast and is maintained at an elevated temperature to maintain its surface finish and structural integrity. The cast core is inserted into the dies of a metal die casting machine to facilitate casting a metal product having internal forms not otherwise attainable. The core is removed from the metal product by simply dissolving and flushing the core out of the casting. The salt material may be reclaimed by a de-salination process for further use.