公开(公告)号：EP0610452A1

公开(公告)日：1994-08-17

申请号：EP93909342.0

申请日：1992-10-29

申请人： I-CUBE DESIGN SYSTEMS, INC. ,  PIE DESIGN SYSTEMS, INC.

发明人： JENQ, Yih-Chyun ,  LOFSTROM, Keith

IPC分类号： H03K19 ,  H03K5 ,  H04L5

CPC分类号： H03K5/026

摘要： Un répéteur (10) de bus bidirectionnel comprend deux répéteurs (11, 13) de bus unidirectionnels connectés pour retransmettre des signaux dans des sens opposés entre deux bus (12, 14). Lorsqu'un circuit d'attaque de bus externe fait descendre la tension de n'importe quel bus, un des répéteurs de bus unidirectionnel fait descendre la tension de l'autre bus. Lorsque le circuit d'attaque de bus externe permet au bus de s'élever au niveau logique élevé, le répéteur de bus unidirectionnel fournit temporairement un courant de charge élevé à l'autre bus afin de le faire monter rapidement en tension. Chaque répéteur de bus unidirectionnels (11, 13) génère également des signaux indiquant lorsqu'il fait monter ou descendre activement son bus de sortie en tension, et les signaux indicateurs empêchent un répéteur de bus unidirectionnel d'attaquer activement sa sortie lorsque l'autre répéteur de bus unidirectionnel attaque activement sa sortie.

公开(公告)号：EP0610452A4

公开(公告)日：1995-06-07

申请号：EP93909342

申请日：1992-10-29

申请人： I CUBE DESIGN SYSTEMS INC ,  PIE DESIGN SYSTEMS INC

发明人： JENQ YIH-CHYUN ,  LOFSTROM KEITH

IPC分类号： H03K19/0175 ,  H03K5/02 ,  H04L5/16 ,  H03K17/16

CPC分类号： H03K5/026

公开(公告)号：EP2002400A4

公开(公告)日：2014-10-15

申请号：EP07861273

申请日：2007-03-26

申请人： CADENCE DESIGN SYSTEMS INC

发明人： KOHLI VIKAS ,  CHOUDHARY PARAG

IPC分类号： G06F17/50 ,  G06T15/00

CPC分类号： G06F17/5045 ,  G06F2217/74

公开(公告)号：EP2465047A4

公开(公告)日：2014-01-15

申请号：EP10808859

申请日：2010-08-13

申请人： CADENCE DESIGN SYSTEMS INC

发明人： CHOU CHING-PING ,  KWAN DARREN

IPC分类号： G06F15/173 ,  G06F13/28

CPC分类号： G06F9/526 ,  G06F13/28 ,  G06F2209/522

公开(公告)号：EP2465039A4

公开(公告)日：2013-01-23

申请号：EP10808858

申请日：2010-08-13

申请人： CADENCE DESIGN SYSTEMS INC

发明人： CHOU CHING-PING ,  HWANG SU-JEN ,  YU TENG-I

IPC分类号： G06F13/28

CPC分类号： G06F13/28

公开(公告)号：EP1327189B1

公开(公告)日：2012-07-25

申请号：EP01981725.3

申请日：2001-10-17

申请人： Cadence Design Systems, Inc.

发明人： HOOVER, Christopher

IPC分类号： G06F7/62 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： A method for hierarchical specification and modeling of scheduling in systemlevel simulations. A static scheduler is synthesized by a Virtual Component Codesign (VCC) process and comprises a simple sequential execution of the run functions (1-3) of behavious A-F. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. Two orthogal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol. The protocol itself is implemented by a pair of abstract interfaces, which in turn are implemented in concrete schedulable and scheduler objects in the simulator.

公开(公告)号：EP2249381A1

公开(公告)日：2010-11-10

申请号：EP09712660.1

申请日：2009-02-16

申请人： Liquid Design Systems, Inc.

发明人： MABUCHI, Yoshihiro

IPC分类号： H01L21/822 ,  H01L21/60 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04

CPC分类号： H01L23/50 ,  H01L24/14 ,  H01L24/32 ,  H01L24/45 ,  H01L25/18 ,  H01L2224/13099 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/01094 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： To provide a sem conductor chip whose number of electrodes are minimized while the horizontal position between the semiconductor chip and the mounted substrate is maintained in implementation to avoid any connection problem, as well as to prevent the damage to the semiconductor circuit of such chip.
For example, there is a cross-shaped connection bump disposition area 23 which is formed by memory banks 22A-22D which face with each other with a certain distance. And in the area 23A in the cross-shaped connection bump disposition area 23, signal input output connection bumps 21A (the first electrodes) are disposed and form a group. On the other hand, by disposing a group of power/grounding connection bumps 21 B in the area 23B which crosses in the right angle with the area 23A where a group of the signal input output connection bumps 21A is disposed, forming a group, the memory chip 20 is supported by the power/grounding bumps 21B (via soldering) so that it will not tilt when implemented on the wiring chip 10, thus, its horizontal position is maintained by the minimum number of bumps. For example, the memory chip 20 is composed as such.

摘要翻译： 为了提供半导体芯片和安装基板之间的水平位置被保持在最小限度的电极数量的半导体芯片，以避免任何连接问题，以及防止对这种芯片的半导体电路的损坏。 例如，存在由相互面对一定距离的存储体22A-22D形成的十字形连接突起配置区域23。 并且在十字形连接凸块配置区域23的区域23A中，设置信号输入输出连接凸块21A（第一电极）并形成组。 另一方面，通过将一组电源/接地连接凸块21B布置在与设置有一组信号输入输出连接凸块21A的区域23A成直角交叉的区域23B中，形成组， 存储芯片20由电源/接地凸块21B（通过焊接）支撑，使得当在布线芯片10上实现时不会倾斜，因此其水平位置由最小的凸块数量保持。 例如，存储芯片20也是这样构成的。

公开(公告)号：EP1521188A3

公开(公告)日：2010-09-29

申请号：EP04256124.1

申请日：2004-10-04

申请人： Cadence Design Systems, Inc.

发明人： Ling, Feng ,  Dengi, Enis Aykut ,  Okhmatovski, Vlamidir I.

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G06F17/5036 ,  G06F2217/78

摘要： To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer is determined from the scalar charge elements in all of the circuit layers. For each circuit layer, the first and second distributions of voltages induced therein are combined to determine an actual distribution of voltages in the circuit layer.

公开(公告)号：EP1966730A4

公开(公告)日：2010-08-25

申请号：EP06845720

申请日：2006-12-18

申请人： CADENCE DESIGN SYSTEMS INC

发明人： WATANABE YOSINORI ,  LAVAGNO LUCIANO ,  KONDRATYEV ALEX

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505

公开(公告)号：EP2204738A3

公开(公告)日：2010-07-28

申请号：EP09015071.5

申请日：2009-12-04

申请人： Cadence Design Systems, Inc.

发明人： Andrews, Jason, Robert

IPC分类号： G06F11/36 ,  G06F17/50

CPC分类号： G06F11/3688 ,  G06F17/5022

摘要： Described is a method, system, and computer program product that provides control of a hardware/software system, and allows deterministic execution of the software under examination. According to one approach, a virtual machine for testing software is used with a lightly synchronized stimulus for the software being tested. A verification tool external to the virtual machine is used to provide test stimulus to and to collect test information from the virtual machine. Test stimulus from the verification tool that is external to the virtual machine provides the stimulation that incrementally operates and changes the state of the virtual machine The stimulus is created and coverage is collected from outside the virtual machine by first stopping the virtual machine, depositing stimulus, and then reading coverage directly from the virtual machine memory while the machine is stopped.