Clock recovery pll for ATM networks
    1.
    发明公开
    Clock recovery pll for ATM networks 审中-公开
    自动柜员机中的PLL zurTaktrückgewinnung

    公开(公告)号:EP1109349A2

    公开(公告)日:2001-06-20

    申请号:EP00311217.4

    申请日:2000-12-15

    申请人: Mitel Corporation

    IPC分类号: H04L7/00 H04L12/56 H04J3/06

    摘要: The invention relates to packet switched networks, and more particularly to a circuit and a method for clock recovery in cell-relay networks, particularly ATM (Asynchronous Transfer Mode) networks offering constant bit rate services. The multimode clock recovery circuit has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

    摘要翻译: 本发明涉及分组交换网络,更具体地说,涉及一种在小区中继网络中,特别是提供恒定比特率服务的ATM(异步传输模式)网络中的时钟恢复的电路和方法。 多模时钟恢复电路具有嵌入式数字锁相环,其包括能够从至少两种类型的输入信号产生相位信号的输入电路。 控制锁相环输出的相位信号产生恒定比特率服务的时钟信号。

    Integrated processing for an etch module using a hard mask technique
    2.
    发明公开
    Integrated processing for an etch module using a hard mask technique 失效
    采用硬掩模技术的蚀刻模块的集成处理

    公开(公告)号:EP0855737A2

    公开(公告)日:1998-07-29

    申请号:EP97310627.1

    申请日:1997-12-24

    申请人: MITEL CORPORATION

    IPC分类号: H01L21/033 H01L21/31

    摘要: A method of fabricating a semiconductor device includes etching hcles through at least one deposited layer to an underlying structure. A hard mask is deposited on an upper surface of a device to be etched, the mask is patterned with the aid of a photoresist and holes are etched in the hard mask. After removal of the photoresist, contact or via holes are etched through the patterned hard mask in the deposited layer(s) to reach the underlying structure.

    摘要翻译: 制造半导体器件的方法包括通过至少一个沉积层蚀刻至下面的结构。 将硬掩模沉积在要被蚀刻的器件的上表面上,借助光刻胶对掩模进行图案化,并且在硬掩模中蚀刻出空穴。 去除光刻胶之后,通过沉积层中的图案化硬掩模蚀刻接触孔或通孔以到达下面的结构。

    START-STOP RECEIVER
    3.
    发明授权
    START-STOP RECEIVER 失效
    START-STOP接收机

    公开(公告)号:EP0707766B1

    公开(公告)日:1997-06-04

    申请号:EP94920350.9

    申请日:1994-07-04

    申请人: MITEL CORPORATION

    IPC分类号: H04L25/40

    CPC分类号: H04L25/40

    摘要: A method is disclosed for extracting data words from a binary serial bit stream having a fixed bit rate and consisting of fixed length words of n bits each, where n is an integer, each word is preceded by a start bit and followed by one or more stop bits. First a predetermined identifiable transition is detected in said bit stream preceding each data word. A clock signal (DCLK) consisting of n clock pulses is generated in response to each detection of the predetermined transition in coincidence with the bits of the data word following the predetermined transition. A data ready signal (DR) is generated after the passage of n bits to delineate the word boundary, and the data words are extracted from the bit stream using the thus generated clock pulses and the data ready signal.

    CELL RELAY TRANSPORT MECHANISM
    4.
    发明公开
    CELL RELAY TRANSPORT MECHANISM 失效
    信元中继传输机制

    公开(公告)号:EP0754397A1

    公开(公告)日:1997-01-22

    申请号:EP95914259.0

    申请日:1995-04-04

    申请人: MITEL CORPORATION

    IPC分类号: H04Q3 H04L12 H04Q11

    摘要: A telecommunications system comprises a plurality of servers interconnected by a TDM backbone and able to share a common channel or bandwith. An arrangement for sending messages or files between said servers comprises a master node for sending a continuous stream of cells round the backbone, each cell having a header portion and a payload portion, and a plurality of downstream nodes which upon arrival of incoming cells insert information therein, read information therefrom, or allow the cells to pass thereby unaltered.

    START-STOP RECEIVER
    5.
    发明公开
    START-STOP RECEIVER 失效
    START-STOPEMPFÄNGER

    公开(公告)号:EP0707766A1

    公开(公告)日:1996-04-24

    申请号:EP94920350.0

    申请日:1994-07-04

    申请人: MITEL CORPORATION

    IPC分类号: H04L27 H04L25

    CPC分类号: H04L25/40

    摘要: A method is disclosed for extracting data words from a binary serial bit stream having a fixed bit rate and consisting of fixed length words of n bits each, where n is an integer, each word is preceded by a start bit and followed by one or more stop bits. First a predetermined identifiable transition is detected in said bit stream preceding each data word. A clock signal (DCLK) consisting of n clock pulses is generated in response to each detection of the predetermined transition in coincidence with the bits of the data word following the predetermined transition. A data ready signal (DR) is generated after the passage of n bits to delineate the word boundary, and the data words are extracted from the bit stream using the thus generated clock pulses and the data ready signal.

    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG
    6.
    发明授权
    MULTI-LEVEL INTERCONNECTION CMOS DEVICES WITH SOG 失效
    具有SOG的多电平互连CMOS器件

    公开(公告)号:EP0551306B1

    公开(公告)日:1995-12-13

    申请号:EP91916654.6

    申请日:1991-09-25

    申请人: MITEL CORPORATION

    发明人: OUELLET, Luc

    摘要: A method of manufacturing a semiconductor wafer, comprises depositing a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, performing a first metallization to deposit a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, performing an in-situ desorption of physically and chemically water vapour in a dry environment at a temperature of at least 400 °C and not more than 550 °C for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25 °C the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, etching via holes through the dielectric and spin-on glass layers to reach the tracks of the first interconnect layer, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks while maintaining the dry environment. The subsequent etching and metallization steps after the desorption step are performed without re-exposure of the wafer to ambient conditions. This technique permits the reliable use of inorganic or quasi-inorganic spin-on glasses in non batch type sputtering equipment.

    摘要翻译: 一种制造半导体晶片的方法,包括在衬底上沉积第一层互连材料,蚀刻互连材料以形成互连线路,执行第一金属化以在互连线路上沉积第一低温介电层,平坦化第一低 通过非深腐蚀工艺在准无机或无机旋涂玻璃上沉积高温介电层,在旋涂玻璃上沉积第二低温介电层,在干燥环境中进行物理和化学水蒸汽的原位解吸 在至少400℃且不超过550℃的温度下持续足以获得可忽略不计的解吸速率的时间,温度超过晶片表面将暴露于其中的温度至少25℃ 随后的金属化步骤,蚀刻穿过介电层和旋涂玻璃层的通孔以到达第一互连层的轨道, 以及执行随后的金属化步骤以将延伸穿过所述通孔的第二互连层沉积到所述第一互连迹线,同时保持所述干燥环境。 在解吸步骤之后进行后续的蚀刻和金属化步骤,而不会将晶片重新暴露在环境条件下。 该技术允许在非间歇式溅射设备中可靠地使用无机或准无机旋涂玻璃。

    PREVENTING OF VIA POISONING BY GLOW DISCHARGE INDUCED DESORPTION
    7.
    发明公开
    PREVENTING OF VIA POISONING BY GLOW DISCHARGE INDUCED DESORPTION 失效
    保护单元通过平衡由辉光放电诱导解吸手段。

    公开(公告)号:EP0563113A1

    公开(公告)日:1993-10-06

    申请号:EP92900971.0

    申请日:1991-12-18

    申请人: MITEL CORPORATION

    发明人: OUELLET, Luc

    IPC分类号: C23C14 H01L21

    CPC分类号: H01L21/31058

    摘要: On décrit un procédé de fabrication de tranches à semi-conducteurs à plusieurs niveaux comprenant une couche d'aplanissement de verre appliquée par centrifugation. Avant que ne soit effectuée la métallisation sous vide de la couche d'interconnexion, et après l'application de la couche appliquée par centrifugation, la tranche est exposée à une décharge luminescente intense d'une telle façon qu'elle est bombardée sous au moins un vide partiel par des ions et/ou des électrons et/ou des photons alors qu'elle se trouve à une température comprise entre 400 °C et 550 °C, et qui est supérieure de 25 °C au moins à la température à laquelle est soumise la tranche au cours de l'étape de métallisation suivante. De cette manière, des molécules indésirables peuvent être désorbées à partir de la couche de verre appliquée par centrifugation de sorte qu'elles ne perturbent pas l'étape de métallisation ultérieure.

    TWIN-TUB FABRICATION METHOD
    8.
    发明公开
    TWIN-TUB FABRICATION METHOD 失效
    的生产方法双接收器。

    公开(公告)号:EP0561909A1

    公开(公告)日:1993-09-29

    申请号:EP92900803.0

    申请日:1991-12-11

    申请人: MITEL CORPORATION

    发明人: HUET, Pierre

    IPC分类号: H01L21 H01L27

    CPC分类号: H01L21/823892 H01L27/0928

    摘要: Procédé permettant de produire des caissons jumelés à alignement automatique (8, 9) de conductivités opposées dans un substrat semi-conducteur (1). Le procédé consiste à implanter une impureté d'un certain type de conductivité dans ledit substrat sur la zone qui formera les caissons jumelés, à masquer le substrat pour n'exposer que la zone sélectionnée (4) de celui-ci qui formera l'un des caissons, à corroder la zone exposée du substrat pour en enlever au moins la majeure partie de l'implant initial (7), à implanter dans la zone exposée du substrat une impureté (5) de conductivité opposée, et à fixer par diffusion thermique les impuretés implantées dans le substrat (1) pour former les caissons jumelés. Ce procédé permet de réduire le nombre d'étapes nécessaires dans le procédé de fabrication ainsi que le nombre d'imperfections cristallines.