公开(公告)号：EP2763177A1

公开(公告)日：2014-08-06

申请号：EP14153839.7

申请日：2014-02-04

Applicant: STmicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Niebojewski, Heimanu ,  Morand, Yves ,  Le Royer, Cyrille

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: L'invention concerne un transistor MOS comprenant, au-dessus d'un isolant de grille (4), un empilement conducteur de grille (6-7) ayant une hauteur, une longueur et une largeur, cet empilement ayant une partie basse (6) voisine de l'isolant de grille et une partie haute (7 ; 27 ; 50), dans lequel ledit empilement a une première longueur (L1) dans sa partie basse, et une deuxième longueur (L2) inférieure à la première longueur dans sa partie haute.

Abstract translation: 晶体管具有导电栅堆叠，其包括靠近栅极绝缘体（4）的下部和上部。 堆叠的上部和下部包括两个不同的长度，其中上部长度比下部长度短。 上部长度为下部长度的0.3〜0.9倍左右。 该叠层与限定真空间隔物（10）的电介质间隔物相邻。 下部包括金属层的一部分，并且上部包括掺杂半导体层的一部分。 堆叠的下部包括掺杂多晶硅层的层，并且上部包括掺杂的多晶硅 - 锗层。 还包括用于制造MOS晶体管的方法的独立权利要求。

公开(公告)号：EP1683187B1

公开(公告)日：2011-06-08

申请号：EP04810633.0

申请日：2004-11-09

Applicant: International Business Machines Corporation

Inventor： DORIS, Bruce, B., c/o IBM United Kingdom Limited ,  BELYANSKY, Michael, P. ,  BOYD, Diane, C. ,  CHIDAMBARRAO, Dureseti ,  GLUSCHENKOV, Oleg

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP2132780A1

公开(公告)日：2009-12-16

申请号：EP08799738.3

申请日：2008-03-31

Applicant: Vishay-Siliconix

Inventor： LI, Jian ,  CHEN, Kuo-in ,  TERRIL, Kyle

IPC: H01L29/78

CPC classification number: H01L29/66734 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7813

Abstract: A trench metal-oxide-semiconductor field effect transistor (MOSFET) (100), includes a drain region (150,155), gate regions (125) disposed above the drain region, gate insulator regions (130) each disposed about a periphery of a respective gate region, a plurality of source regions (120) disposed in recessed mesas between gate insulator regions, a plurality of body regions (145) disposed in said recessed mesas between gate insulator regions and between source regions and the drain region. The MOSFET also includes body contact regions (147) each disposed in a respective body region, source/body contact spacers (140) disposed between gate insulator regions above the recessed mesas, a source/body contact (110) disposed above the source/body contact spacers, and source/body contact plugs (115) disposed between the source/body contact spacers and coupling the source/body contact to the body contact regions and the source regions.

公开(公告)号：EP1451877A4

公开(公告)日：2009-06-03

申请号：EP02786713

申请日：2002-11-13

Applicant: GEN SEMICONDUCTOR INC

Inventor： HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/513 ,  H01L29/7813

Abstract: A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

公开(公告)号：EP1571711A1

公开(公告)日：2005-09-07

申请号：EP03797945.7

申请日：2003-09-18

Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

Inventor： KITAGUCHI, Makoto, Factory of Shindengen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66681 ,  H01L21/823857 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/7816

Abstract: A lateral short-channel DMOS 10A according to the present invention includes an N--type epitaxial layer 110 formed on a surface of a P--type semiconductor substrate 108, a P-type well 114 that is formed in a surface of the N--type epitaxial layer 110 and includes a channel forming region C, an N+-type source region 116 formed in a surface of the P-type well 114, an ON resistance lowering N-type well 134 formed in a surface of the N--type epitaxial layer 110 so as to not contact the P-type well 114, an N+-type drain region 118 formed in a surface of the ON resistance lowering N-type well 134, a polysilicon gate electrode 122 formed via a gate insulating film 120 in at least an upper part of the channel forming region C out of a region from the N+-type source region 116 to the N+-type drain region 118, and a gate resistance lowering metal layer 130 connected to the polysilicon gate electrode 122.
The lateral short-channel DMOS 10A according to the present invention therefore has a low gate resistance and a low ON resistance, as well as superior high-speed switching characteristics and superior current driving characteristics.

Abstract translation: 根据本发明的横向短沟DMOS 10A包括形成在P型半导体衬底108的表面上的N型外延层110，形成在N型表面的P型阱114 型外延层110，包括沟道形成区C，形成在P型阱114的表面中的N +型源极区116，形成在N型阱区的表面上的导通电阻降低N型阱134。 型外延层110，以不与P型阱114接触，形成在导通电阻降低N型阱134的表面中的N +型漏区118，经由栅极绝缘膜形成的多晶硅栅电极122 120，在从N +型源极区域116到N +型漏极区域118的区域中的沟道形成区域C的至少上部，以及连接到多晶硅栅电极122的栅极电阻降低金属层130。 因此，根据本发明的横向短通道DMOS 10A具有lo W栅极电阻和低导通电阻，以及优异的高速开关特性和优异的电流驱动特性。

公开(公告)号：EP1451877A1

公开(公告)日：2004-09-01

申请号：EP02786713.4

申请日：2002-11-13

Applicant: GENERAL SEMICONDUCTOR, Inc.

Inventor： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/513

Abstract: A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

公开(公告)号：EP1266407A2

公开(公告)日：2002-12-18

申请号：EP01912755.4

申请日：2001-02-15

Applicant: GENERAL SEMICONDUCTOR, Inc.

Inventor： HSHIEH, Fwu-luan ,  SO, Koon, Chong

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

公开(公告)号：EP1253632A2

公开(公告)日：2002-10-30

申请号：EP02015293.0

申请日：1995-12-21

Applicant: INTEL CORPORATION

Inventor： Chau, Robert S. ,  Packan, Paul A. ,  Chern, Chan-Hong ,  Yau, Leopoldo D. ,  Jan, Chia-Hong ,  Weldon, Kevin R.

IPC: H01L21/336 ,  H01L21/225

CPC classification number: H01L29/0847 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A novel transistor (200) with a low resistance ultra shallow tip region (214) and its method of fabrication. The novel transistor of the present invention has a source/drain extension of tip region (210) comprising an ultra shallow region (214) which extends beneath the gate electrode and a raised region (216).

公开(公告)号：EP0715769B1

公开(公告)日：2002-03-06

申请号：EP94923248.2

申请日：1994-06-24

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： DEMIRLIOGLU, Esin, Kutlu ,  ARONOWITZ, Sheldon

IPC: H01L21/225 ,  H01L21/82 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/823835 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/66545

Abstract: A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.

公开(公告)号：EP0287031B1

公开(公告)日：1995-02-01

申请号：EP88105805.1

申请日：1988-04-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA MICRO-ELECTRONICS CORPORATION

Inventor： Mikata, Yuuichi c/o Patent Division ,  Ishihara, Katsunori

IPC: H01L29/41 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L29/43 ,  H01L29/4925