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公开(公告)号:EP1288961A3
公开(公告)日:2004-03-24
申请号:EP02252317.9
申请日:2002-03-28
申请人: FUJITSU LIMITED
发明人: Yamaguchi, Shusaku , Uchida, Toshiya , Yagishita, Yoshimasa , Bando, Yoshihide , Yada, Masahiro , Okuda, Masaki , Kobayashi, Hiroyuki , Hara, Kota , Fujioka, Shinya , Fujieda, Waichiro
IPC分类号: G11C11/406 , G11C7/10 , G11C11/4096
CPC分类号: G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要: A semiconductor memory is provided with a plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command (WRA) and the refresh command (REFRQ) conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
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公开(公告)号:EP1288961A2
公开(公告)日:2003-03-05
申请号:EP02252317.9
申请日:2002-03-28
申请人: FUJITSU LIMITED
发明人: Yamaguchi, Shusaku , Uchida, Toshiya , Yagishita, Yoshimasa , Bando, Yoshihide , Yada, Masahiro , Okuda, Masaki , Kobayashi, Hiroyuki , Hara, Kota , Fujioka, Shinya , Fujieda, Waichiro
IPC分类号: G11C11/406
CPC分类号: G11C7/1006 , G11C8/12 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4087 , G11C2211/4061 , G11C2211/4062
摘要: A semiconductor memory is provided with a plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command (WRA) and the refresh command (REFRQ) conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.
摘要翻译: 半导体存储器具有用于再现第一存储块的数据的多个第一存储块和第二存储块。 当读取命令和刷新命令彼此冲突时,读取控制电路根据刷新命令访问第一存储器块,并通过使用第二存储器块再现读取数据。 当写入命令(WRA)和刷新命令(REFRQ)彼此冲突时,写入控制电路根据命令接收的顺序操作存储器块。 因此,可以在不被用户识别的情况下执行刷新操作。 即,可以提供用户友好的半导体存储器。
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