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    Memory circuit having parity cell array
    1.
    发明公开
    Memory circuit having parity cell array 有权
    具有奇偶校验单元阵列存储器电路

    公开(公告)号：EP1315176A3

    公开(公告)日：2006-01-11

    申请号：EP02257328.1

    申请日：2002-10-22

    申请人： FUJITSU LIMITED

    发明人： Fujioka, Shinya ,  Fujieda, Waichiro ,  Hara, Kota ,  Koga, Toru ,  Mori, Katsuhiro

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C2211/4062

    摘要： A memory circuit has: a real cell array (RCA); a parity generating circuit (28) for generating a parity bit from data of the real cell array; a parity cell array (PCA); a refresh control circuit (32, 34, 36), which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit (30) for outputting data from the real cell array. Further, the memory circuit has a test control circuit (38), which, in a first test mode, prohibits a refresh operation for the real cell array (RCA) to output data read out from the real cell array, and, in a second test mode, controls the output circuit (30) so as to output data read out from the parity cell array (PCA).

    Memory circuit having parity cell array
    2.
    发明公开
    Memory circuit having parity cell array 有权
    Speicherschaltung mitParitätszellenmatrix

    公开(公告)号：EP1315176A2

    公开(公告)日：2003-05-28

    申请号：EP02257328.1

    申请日：2002-10-22

    申请人： FUJITSU LIMITED

    发明人： Fujioka, Shinya ,  Fujieda, Waichiro ,  Hara, Kota ,  Koga, Toru ,  Mori, Katsuhiro

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C2211/4062

    摘要： A memory circuit has: a real cell array (RCA); a parity generating circuit (28) for generating a parity bit from data of the real cell array; a parity cell array (PCA); a refresh control circuit (32, 34, 36), which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit (30) for outputting data from the real cell array. Further, the memory circuit has a test control circuit (38), which, in a first test mode, prohibits a refresh operation for the real cell array (RCA) to output data read out from the real cell array, and, in a second test mode, controls the output circuit (30) so as to output data read out from the parity cell array (PCA).

    摘要翻译： 存储电路具有：真实单元阵列（RCA）; 用于从所述真实单元阵列的数据产生奇偶校验位的奇偶产生电路（28）; 奇偶校验单元阵列（PCA）; 刷新控制电路（32,34,36），其顺序地刷新所述真实单元阵列，并且当内部刷新请求和读取请求重合时，优先刷新操作; 数据恢复部分，根据从奇偶校验单元阵列读出的奇偶校验位，恢复从真实单元阵列读出的数据; 以及用于从真实单元阵列输出数据的输出电路（30）。 此外，存储器电路具有测试控制电路（38），其在第一测试模式中禁止对真实单元阵列（RCA）的刷新操作以输出从真实单元阵列读出的数据，并且在第二测试 测试模式，控制输出电路（30）以输出从奇偶校验单元阵列（PCA）读出的数据。

    Semiconductor memory
    3.
    发明公开
    Semiconductor memory 有权
    半导体内存

    公开(公告)号：EP1288961A2

    公开(公告)日：2003-03-05

    申请号：EP02252317.9

    申请日：2002-03-28

    申请人： FUJITSU LIMITED

    发明人： Yamaguchi, Shusaku ,  Uchida, Toshiya ,  Yagishita, Yoshimasa ,  Bando, Yoshihide ,  Yada, Masahiro ,  Okuda, Masaki ,  Kobayashi, Hiroyuki ,  Hara, Kota ,  Fujioka, Shinya ,  Fujieda, Waichiro

    IPC分类号： G11C11/406

    CPC分类号： G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： A semiconductor memory is provided with a plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command (WRA) and the refresh command (REFRQ) conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

    摘要翻译： 半导体存储器具有用于再现第一存储块的数据的多个第一存储块和第二存储块。 当读取命令和刷新命令彼此冲突时，读取控制电路根据刷新命令访问第一存储器块，并通过使用第二存储器块再现读取数据。 当写入命令（WRA）和刷新命令（REFRQ）彼此冲突时，写入控制电路根据命令接收的顺序操作存储器块。 因此，可以在不被用户识别的情况下执行刷新操作。 即，可以提供用户友好的半导体存储器。