公开(公告)号：EP0935256B1

公开(公告)日：2002-05-08

申请号：EP99105448.7

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC: G11C29/00 ,  H01L21/02

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0935256A1

公开(公告)日：1999-08-11

申请号：EP99105448.7

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC: G11C29/00 ,  H01L21/02

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: A test method for a writable nonvolatile semiconductor memory, comprising: a writing step for writing data; an aging step wherein the nonvolatile semiconductor memory is placed under prescribed aging conditions; and a verification step where data is read out and compared with the data written in the writing step for verification. The test method is characterised in that the aging step incorporates a step of forming a coating film for alleviating the stress applied to the nonvolatile semiconductor memory during assembly.

Abstract translation: 本发明的一个目的是提供一种允许容易和有效测试的半导体器件。 非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及 状态寄存器2，用于在电路9的操作完成时存储存储器的工作状态，其中在存储单元矩阵17的地址外提供两种虚拟单元D1，D2，D3。 它们的值被固定到从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。