摘要:
A photovoltaic device is disclosed including at least one Cadmium Sulfide Telluride (CdS x Te 1-x ) layer as are methods of forming such a photovoltaic device.
摘要:
Embodiments include photovoltaic devices that include at least one absorber layer, e.g. CdTe and/or CdS x Te 1-x (where 0≤x≤1), having an average grain size to thickness ratio from greater than 2 to about 50 and an average grain size of between about 4 µm and about 14 µm and methods for forming the same.
摘要:
A photovoltaic device includes a substrate structure and at least one Se-containing layer, such as a CdSeTe layer. A process for manufacturing the photovoltaic device includes forming the CdSeTe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process can also include controlling a thickness range of the Se-containing layer.
摘要:
A photovoltaic device includes a substrate and has a transparent conductive oxide layer, a conductive back layer, and at least one intermediate semiconductor layer formed thereon. An isolation scribe divides and electrically isolates the oxide layer, the back layer and the semiconductor layer to define two photovoltaic cells. A conductor extends across the isolation scribe and connects the back layer of one photovoltaic cell to the oxide layer of the other photovoltaic cell.
摘要:
A photovoltaic device including a protective layer between a window layer and an absorber layer, the protective layer inhibiting dissolving/intermixing of the window layer into the absorber layer during a device activation step, and methods of forming such photovoltaic devices.
摘要:
Methods and devices are described for a photovoltaic device. The photovoltaic device includes a glass substrate, a semiconductor absorber layer formed over the glass substrate, a metal back contact layer formed over the semiconductor absorber layer, and a p-type back contact buffer layer formed from one of MnTe, Cd1-xMnxTe, and SnTe, the buffer layer disposed between the semiconductor absorber layer and the metal back contact layer.