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公开(公告)号：EP0597307B1
公开(公告)日：1999-04-28
申请号：EP93117256.3
申请日：1993-10-25
发明人： Kawasaki, Shumpei , Fukada, Kaoru , Watabe, Mitsuru , Noguchi, Kouki , Matsubara, Kiyoshi , Mochizuki, Isamu , Suzukawa, Kazufumi , Masumura, Shigeki , Akao, Yasushi , Sakakibara, Eiji
CPC分类号： G06F15/7832 , G06F13/4239 , G06F15/786
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公开(公告)号：EP0597307A1
公开(公告)日：1994-05-18
申请号：EP93117256.3
申请日：1993-10-25
发明人： Kawasaki, Shumpei , Fukada, Kaoru , Watabe, Mitsuru , Noguchi, Kouki , Matsubara, Kiyoshi , Mochizuki, Isamu , Suzukawa, Kazufumi , Masumura, Shigeki , Akao, Yasushi , Sakakibara, Eiji
CPC分类号： G06F15/7832 , G06F13/4239 , G06F15/786
摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH * , CASL * and RAS * for direct connection to a dynamic RAM, and chip select signal output terminals CSO * through CS6 * for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
摘要翻译： 一种易于使用和直接连接到诸如动态和静态RAM以及其他外围电路之类的存储器的微型计算机。 微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号 终端。 微型计算机还包括用于根据需要输出未复用或复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。
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公开(公告)号：EP0902358A2
公开(公告)日：1999-03-17
申请号：EP98120014.0
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
摘要翻译： 采用通用寄存器方法的微型计算机MCU能够使用效率低的系统成本具有小的程序容量或高程序存储器，同时具有简化指令解码的优点，如具有固定长度指令格式的RISC机器 通过采用小于馈送到指令执行装置的最大数据字的长度的2
个固定长度的指令格式。 编码分割的控制是通过注意码位执行的。 -
公开(公告)号：EP0902361A2
公开(公告)日：1999-03-17
申请号：EP98120015.7
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki B-11, Hitachitennouueshataku , Watabe, Mitsuru
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
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公开(公告)号：EP0525375A3
公开(公告)日：1993-04-21
申请号：EP92110517.7
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.
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公开(公告)号：EP0525375A2
公开(公告)日：1993-02-03
申请号：EP92110517.7
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 n bits, whilst the data use size is 2 m bits,where m is greater than or equal to n.
摘要翻译： RISC型微处理器的固定结构长度为2 n位，数据使用大小为2 m，m大于或等于n。
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公开(公告)号：EP0902361B1
公开(公告)日：2004-06-02
申请号：EP98120015.7
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 bits, whilst the data use size is 2 bits,where m is greater than or equal to n.
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公开(公告)号：EP1233447A2
公开(公告)日：2002-08-21
申请号：EP01120671.1
申请日：2001-08-31
申请人： Hitachi, Ltd.
IPC分类号： H01L21/762 , H01L27/088
CPC分类号： H01L27/12 , H01L21/76229 , H01L21/84 , Y10T307/747
摘要： A semiconductor device comprises an embedded insulation layer (101) formed on a semiconductor substrate (100), plural power semiconductor elements (2, 3) formed on a semiconductor substrate (100) on the embedded insulation layer, a trench (4) formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator (5) insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements (2, 3) such as transistors can be used, being connected to each other in series.
摘要翻译： 一种半导体器件，包括形成在半导体衬底（100）上的嵌入绝缘层（101），在所述嵌入绝缘层上的半导体衬底（100）上形成的多个功率半导体元件（2,3），在所述半导体衬底 半导体基板之间以及功率半导体元件与功率半导体元件的绝缘驱动控制电极之间的绝缘以及功率半导体元件（2,3）等晶体管的功率半导体元件（2,3）之间的绝缘，可以使用彼此连接 串联。
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公开(公告)号：EP0902361A3
公开(公告)日：2002-01-02
申请号：EP98120015.7
申请日：1992-06-22
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
摘要翻译： 采用通用寄存器方法的微型计算机MCU能够具有小的程序容量或高程序存储器使用效率和低系统成本，同时享有如具有固定长度指令格式的RISC机器中的简化指令解码的优点 通过采用比输入指令执行装置的最大数据字的长度小的固定长度2n比特的指令格式， 编码部分的控制是通过记录码位来执行的。
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10.发明公开Data processing system and image processing system 失效Datenverarbeitungssystem和Bildverarbeitungssystem。
公开(公告)号：EP0649100A2
公开(公告)日：1995-04-19
申请号：EP94115140.9
申请日：1994-09-26
申请人： HITACHI, LTD.
发明人： Satoh, Jun , Yamagishi, Kazushige , Nakashima, Keisuke , Katsura, Koyo , Miyamoto, Takashi , Watabe, Mitsuru , Ohmura, Kenichiroh
CPC分类号： G09G5/393 , G06F1/04 , G06F1/12 , G06F12/0207 , G06F13/1689 , G06F13/4243 , G06F15/7832 , G06T1/60 , G09G5/001 , G09G5/395 , G09G5/399 , G09G2320/0252 , G09G2350/00 , G09G2360/128 , G09G2370/10 , G11C8/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C8/18
摘要： A data processor comprises a bus control circuit (14) adapted to be interfaced with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal (CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit (14) for producing data and addresses for accessing a memory (22), and a clock driver (16) for feeding intrinsic operation clocks to said data processing modules (12, 13) and for feeding the clock signal for accessing said memory (22) in synchronism with the operations of said data processing modules (12, 13) to be operated by the operation clock signals, to the outside.
摘要翻译： 数据处理器包括适于与可与时钟信号（CLK）同步访问的同步DRAM（22）接口的总线控制电路（14），与所述时钟信号（CLK）耦合的多个数据处理模块（12,13） 总线控制电路（14），用于产生用于访问存储器（22）的数据和地址;以及时钟驱动器（16），用于将固有操作时钟馈送到所述数据处理模块（12,13），并且用于馈送用于访问所述存储器 存储器（22）与由操作时钟信号操作的所述数据处理模块（12,13）的操作同步到外部。
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