利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.017 秒)

    Microprocessor and method for setting up its peripheral functions
    7.
    发明公开
    Microprocessor and method for setting up its peripheral functions 失效
    微处理器和设置其外设功能的方法

    公开(公告)号：EP0740254A3

    公开(公告)日：1996-11-20

    申请号：EP96112686.9

    申请日：1990-12-07

    申请人： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORPORATION

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Miwa, Yoshiyuki ,  Sawase, Terumi ,  Sato, Yuji ,  Masumura, Shigeki

    IPC分类号： G06F13/12 ,  G06F9/38 ,  G06F15/78

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

    摘要翻译： 单片微处理器1包括一个CPU2和一个用于通过软件实现微处理器1的外围功能的子处理器5。 子处理器5包括称为微程序存储单元13的电可写内部存储设备和用于存储软件的顺序控制存储单元62。 可以通过将软件写入存储器单元13和62来定义或修改要由子处理器5实现的外围功能。因此，定义或修改外围功能所花费的时间与编程所花费的时间相同 存储器单元13和62.子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址给微程序存储单元13以提供微指令的地址控制电路14 到执行单元16.序列控制存储器单元62是地址控制电路14的一部分，其也包括多个地址寄存器MAR0到MAR11。 序列控制存储单元62用于存储多个地址寄存器MAR0至MAR11将按顺序选择的顺序的信息。 在序列控制存储器单元62上执行的每个读取周期中选择地址寄存器MAR0至MAR11中的一个。然后，将存储在选择的地址寄存器MAR0至MAR11中的微型地址提供给微程序存储器单元13.任务空值信息 也可以存储在序列控制存储单元62中。在每个读取周期中选择地址寄存器MAR0至MAR11中的一个允许子处理器5以事件驱动为基础进行操作。

    Microcomputer and microcomputer system
    8.
    发明公开
    Microcomputer and microcomputer system 失效
    Mikrocomputer和Mikrocomputersystem。

    公开(公告)号：EP0597307A1

    公开(公告)日：1994-05-18

    申请号：EP93117256.3

    申请日：1993-10-25

    申请人： HITACHI, LTD. ,  HITACHI MICROCOMPUTER SYSTEM LTD. ,  HITACHI VLSI ENGINEERING CORPORATION

    发明人： Kawasaki, Shumpei ,  Fukada, Kaoru ,  Watabe, Mitsuru ,  Noguchi, Kouki ,  Matsubara, Kiyoshi ,  Mochizuki, Isamu ,  Suzukawa, Kazufumi ,  Masumura, Shigeki ,  Akao, Yasushi ,  Sakakibara, Eiji

    IPC分类号： G06F13/42 ,  G06F15/78

    CPC分类号： G06F15/7832 ,  G06F13/4239 ,  G06F15/786

    摘要： A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH * , CASL * and RAS * for direct connection to a dynamic RAM, and chip select signal output terminals CSO * through CS6 * for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.

    摘要翻译： 一种易于使用和直接连接到诸如动态和静态RAM以及其他外围电路之类的存储器的微型计算机。 微型计算机具有选通信号输出端子CASH *，CASL *和RAS *，用于直接连接到动态RAM，以及芯片选择信号输出端子CS0 *至CS6 *，用于与选通信号输出的输出并行输出芯片选择信号 终端。 微型计算机还包括用于根据需要输出未复用或复用的地址信号的地址输出端子和用于选择性地输出地址信号以符合多总线接口方案的数据I / O端子。