公开(公告)号：EP1905074A4

公开(公告)日：2012-06-27

申请号：EP06773946

申请日：2006-06-26

申请人： IBM

发明人： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC分类号： H01L21/84 ,  H01L27/108 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

公开(公告)号：EP2401761A4

公开(公告)日：2012-04-25

申请号：EP10780978

申请日：2010-05-04

申请人： IBM

发明人： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC分类号： H01L21/8244 ,  H01L21/8234 ,  H01L27/11

CPC分类号： H01L27/0207 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104

公开(公告)号：EP1639648A4

公开(公告)日：2007-05-30

申请号：EP04777432

申请日：2004-06-30

申请人： IBM

发明人： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC分类号： H01L29/06 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

公开(公告)号：EP2281303A4

公开(公告)日：2013-11-20

申请号：EP09798429

申请日：2009-06-18

申请人： IBM

发明人： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC分类号： H01L21/334 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

公开(公告)号：EP1692724A4

公开(公告)日：2007-11-21

申请号：EP03796818

申请日：2003-12-08

申请人： IBM

发明人： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC分类号： H01L27/148 ,  H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.