公开(公告)号：EP1690294A4

公开(公告)日：2010-09-22

申请号：EP04810448

申请日：2004-11-05

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795

公开(公告)号：EP1908111A4

公开(公告)日：2008-09-03

申请号：EP06788064

申请日：2006-07-21

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BREITWISCH MATTHEW J ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L29/12 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate (101 ); a silicon germanium (SiGe) layer (103) over the substrate (103); a semiconductor layer (105) over and adjacent to the SiGe layer (103); an insulating layer (109a) adjacent to the substrate (101), the SiGe layer (103), and the semiconductor layer (105); a pair of first gate structures (111) adjacent to the insulating layer (1 09a); and a second gate structure (113) over the insulating layer (109a). Preferably, the insulating layer (109a) is adjacent to a side surface of the SiGe layer (103) and an upper surface of the semiconductor layer (105), a lower surface of the semiconductor layer (105), and a side surface of the semiconductor layer (105). Preferably, the SiGe layer (103) comprises carbon. Preferably, the pair of first gate structures (111) are substantially transverse to the second gate structure (113). Additionally, the pair of first gate structures (111) are preferably encapsulated by the insulating layer (109a).

Abstract translation: 一种场效应晶体管（FET）及其形成方法，包括衬底（101）; 在衬底（103）上的硅锗（SiGe）层（103）; 在所述SiGe层（103）上方并且与所述SiGe层（103）相邻的半导体层（105）; 与衬底（101），SiGe层（103）和半导体层（105）相邻的绝缘层（109a）; 一对第一栅极结构（111），与绝缘层（109a）相邻; 和在绝缘层（109a）上的第二栅极结构（113）。 优选地，绝缘层（109a）与SiGe层（103）的侧表面和半导体层（105）的上表面，半导体层（105）的下表面以及半导体层 半导体层（105）。 优选地，SiGe层（103）包含碳。 优选地，该对第一栅极结构（111）基本上横向于第二栅极结构（113）。 此外，一对第一栅极结构（111）优选由绝缘层（109a）封装。

公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：EP1573804A4

公开(公告)日：2006-03-08

申请号：EP02798557

申请日：2002-12-19

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66795

Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124) , and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

公开(公告)号：EP2404316A4

公开(公告)日：2016-04-06

申请号：EP10770142

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：EP1905074A4

公开(公告)日：2012-06-27

申请号：EP06773946

申请日：2006-06-26

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

公开(公告)号：EP1792346A4

公开(公告)日：2009-09-09

申请号：EP05805693

申请日：2005-09-19

Applicant: IBM

Inventor： ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/737 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/0653 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：EP1586108A4

公开(公告)日：2009-03-04

申请号：EP02798556

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD J

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/11 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66765 ,  H01L29/785

Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118) and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.

公开(公告)号：EP1620891A4

公开(公告)日：2007-03-28

申请号：EP04707026

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.