公开(公告)号：EP1695381A4

公开(公告)日：2008-09-17

申请号：EP03796637

申请日：2003-12-04

Applicant: IBM

Inventor： DOKUMACI OMER H ,  RONSHEIM PAUL

IPC: H01L21/8242 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device includes defining a sacrificial layer (108) over a single crystalline substrate (106). The sacrificial layer (108) is implanted with a dopant species in a manner that prevents the single crystalline substrate (106) from becoming substantially amorphized. The sacrificial layer (108) is annealed so as to drive said dopant species from said sacrificial layer (108) into said single crystalline substrate (106).

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1685584A4

公开(公告)日：2008-12-31

申请号：EP04756373

申请日：2004-06-30

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) (25) in a substrate and providing a first material (30) and a second material (40) on the substrate. The first material (30) and the second material (40) are mixed into the substrate by a thermal anneal process to form a first island (50) and second island (55) at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island (50) and the second island (55). The STI relaxes and facilitates the relaxation of the first island (50) and the second island (55). The first material (30) may be deposited or grown Ge material and the second material (40) may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island (50) and the second island (55).