公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：EP2145349A4

公开(公告)日：2012-03-28

申请号：EP08754077

申请日：2008-04-08

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  HENSON WILLIAM K ,  YAN HONGWEN ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

公开(公告)号：EP1825509A4

公开(公告)日：2009-04-15

申请号：EP05853786

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：EP1565931A4

公开(公告)日：2006-04-19

申请号：EP02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

公开(公告)号：EP2250123A4

公开(公告)日：2014-10-15

申请号：EP09709244

申请日：2009-02-03

Applicant: IBM

Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

IPC: B82B3/00 ,  B81C1/00

CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

公开(公告)号：EP2235743A4

公开(公告)日：2013-03-20

申请号：EP09704665

申请日：2009-01-15

Applicant: IBM

Inventor： DALTON TIMOTHY ,  DORIS BRUCE B ,  KIM HO-CHEOL ,  RADENS CARL

IPC: H01L21/033 ,  B81C1/00

CPC classification number: H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

公开(公告)号：EP1974372A4

公开(公告)日：2009-12-09

申请号：EP07716303

申请日：2007-01-03

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.