公开(公告)号：EP1565931A4

公开(公告)日：2006-04-19

申请号：EP02791319

申请日：2002-11-25

Applicant: IBM

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  IEONG MEIKEI ,  MANDELMAN JACK A

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

Abstract: A semiconductor device structure, includes a PMOS device (200) and an NMOS device (300) disposed on a substrate (1, 2) the PMOS device including a compressive layer (6) stressing an active region of the PMOS device, the NMOS device including a tensile layer (9) stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices (200, 300).

公开(公告)号：EP0814507A1

公开(公告)日：1997-12-29

申请号：EP97304339

申请日：1997-06-20

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for forming the active area of the second device.

Abstract translation: 公开了一种用于形成三维器件结构的方法，例如包括形成在第一器件（315）上的第二器件（370）的沟槽电容器DRAM单元。 具有单晶顶表面（350）的层（350,355）形成在第一装置（315）上方，以提供用于形成第二装置的有效区域的基座。

公开(公告)号：EP1977425A4

公开(公告)日：2009-04-29

申请号：EP07710032

申请日：2007-01-10

Applicant: IBM

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：EP1588403A4

公开(公告)日：2010-03-24

申请号：EP04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

公开(公告)号：EP1584108A4

公开(公告)日：2006-06-07

申请号：EP03701269

申请日：2003-01-08

Applicant: IBM

Inventor： MANDELMAN JACK A ,  GAMBINO JEFFREY P ,  WANG GENG

IPC: H01L21/20 ,  H01L21/308 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3081 ,  H01L27/10864

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

公开(公告)号：EP0720218A3

公开(公告)日：1998-12-16

申请号：EP95119309

申请日：1995-12-07

Applicant: SIEMENS AG ,  IBM

Inventor： ALSMEIER JOHANN ,  MANDELMAN JACK A

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/76 ,  H01L29/10

CPC classification number: H01L27/10873 ,  H01L21/823412 ,  H01L29/7838

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850°C gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850°C gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850°C gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850°C gate oxidation step may follow the RTO gate oxidation step.

Abstract translation: 如动态随机存取存储器（DRAM）技术中，用于显着地减少到设备异常埋沟道p-MOSFET灵敏度制造沟槽界定埋沟p型金属氧化物半导体场效应晶体管（P-MOSFET）的，的方法 宽度。 在一个实施方式中，该方法包括深磷n阱注入步骤之后，使用惰性气体的低温退火步骤的开始，和硼埋沟道注入之前和850℃栅极氧化步骤。 可替代地，退火步骤可以在硼埋沟植入物和850℃栅极氧化步骤之前，之后进行。 在另一个实施方式快速热氧化（RTO）的步骤代替了850℃栅极氧化步骤，继深磷n阱和硼埋入沟道注入步骤。 可替换地，在850℃下栅极氧化步骤可跟随RTO栅极氧化步骤。