公开(公告)号：EP1671358A4

公开(公告)日：2009-10-21

申请号：EP04789450

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1695383A4

公开(公告)日：2007-12-12

申请号：EP03819162

申请日：2003-12-16

Applicant: IBM

Inventor： HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ST ONGE A STEPHEN ,  WANG PING-CHUAN

IPC: H01L21/8249 ,  H01L21/768 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors (116) and a plurality of vertical bipolar transistors (118) positioned on a single substrate (110). The vertical bipolar transistors (118) are taller devices than the CMOS transistors (116). In this structure, a passivating layer (112) is positioned above the substrate (110), and between the vertical bipolar transistors (118) and the CMOS transistors (116). A wiring layer (120) is above the passivating layer (112). The vertical bipolar transistors (118) are in direct contact with the wiring layer (120) and the CMOS transistors (116) are connected to the wiring layer (114) by contacts extending through the passivating layer (112).

公开(公告)号：EP1792343A4

公开(公告)日：2009-11-11

申请号：EP05754954

申请日：2005-05-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/20 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

公开(公告)号：EP1794778A4

公开(公告)日：2009-06-03

申请号：EP05779566

申请日：2005-08-04

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.