公开(公告)号：EP2580782A4

公开(公告)日：2014-10-01

申请号：EP11810114

申请日：2011-06-29

Applicant: IBM

Inventor： ANDERSON FREDERICK G ,  LARY JENIFER E ,  RASSEL ROBERT M ,  STIDHAM MARK E

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/66143

公开(公告)号：EP2377158A4

公开(公告)日：2014-01-15

申请号：EP09835569

申请日：2009-12-15

Applicant: IBM

Inventor： COLLINS DAVID S ,  RASSEL ROBERT M ,  THOMPSON ERIC

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0805 ,  H01L27/0808 ,  H01L29/66181 ,  H01L29/945

公开(公告)号：EP2168163A4

公开(公告)日：2012-08-01

申请号：EP08771894

申请日：2008-06-25

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  JOHNSON JEFFREY B ,  PHELPS RICHARD A ,  RASSEL ROBERT M ,  ZIERAK MICHAEL L

IPC: H01L29/808 ,  H01L21/337 ,  H01L29/36

CPC classification number: H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

公开(公告)号：EP1979949A4

公开(公告)日：2010-08-25

申请号：EP07710011

申请日：2007-01-09

Applicant: IBM

Inventor： CHENG KANGGUO ,  RASSEL ROBERT M

IPC: H01L29/94 ,  H01L21/02 ,  H01L21/334 ,  H01L27/01 ,  H01L27/06

CPC classification number: H01L29/945 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L29/66181

公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1839340A4

公开(公告)日：2009-09-09

申请号：EP05855611

申请日：2005-12-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  FURKAY STEPHEN S ,  JOHNSON JEFFREY B ,  RASSEL ROBERT M

IPC: H01L21/20 ,  H01L29/93

CPC classification number: H01L29/93

Abstract: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

公开(公告)号：EP1671362A4

公开(公告)日：2010-04-28

申请号：EP04789451

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  GREER HEIDI L ,  RASSEL ROBERT M

IPC: H01L21/02 ,  H01L20060101 ,  H01L21/302 ,  H01L21/461 ,  H01L27/07 ,  H01L27/08

CPC classification number: H01L27/0738 ,  H01L27/0802 ,  H01L28/20

公开(公告)号：EP1794778A4

公开(公告)日：2009-06-03

申请号：EP05779566

申请日：2005-08-04

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

公开(公告)号：EP1800343A4

公开(公告)日：2008-11-19

申请号：EP05782737

申请日：2005-08-05

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  HERSHBERGER DOUGLAS B ,  RASSEL ROBERT M

IPC: H01L29/93 ,  H01L29/94

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).