公开(公告)号：EP1461828A4

公开(公告)日：2005-09-28

申请号：EP02803310

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00

CPC classification number: B81C1/00246 ,  B81B2201/016 ,  B81B2201/018 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0122 ,  B81C2203/0735 ,  H01G5/40 ,  H01H59/0009

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：EP0809302A3

公开(公告)日：1998-12-30

申请号：EP97303448

申请日：1997-05-21

Applicant: IBM

Inventor： SUBBANNA SESHADRI

IPC: H01L21/8249 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1075 ,  H01L29/7394

Abstract: A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well (14), wherein the isolated P-well (14) is adjusted so that it does not extend below the field isolation (32)(e.g., STI) and the width and doping of the P-well (14) and an underlying buried N-well (13) is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device is also provided.

Abstract translation: 与在具有分离的P阱，worin隔离P阱被调整并不会延伸下方的场隔离（例如，STI）和的宽度和掺杂NFET（多个）场隔离包括CMOS集成电路 P阱和下面的掩埋N-阱被调整所做的源极/漏极（SD）二极管的耗尽区，从而阱二极管只是满足（合并），而不在所述P阱重叠。 的半导体器件获得在本体单晶技术双极效应和减少结电容。 因此，提供一种用于半导体器件的制造方法。